3D-NAND flash explores beyond 300 layers at VLSI Symposium
3D-NAND flash non-volatile memory is covered by several papers at the upcoming 2023 Symposium on VLSI Technology and Circuits. The conference is due to take place in Kyoto, Japan, June 11 to 16.
The paper C2-1 from Kioxia Corp., “A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit Density with 3.2Gbps Interface and 205MB/s Program Throughput” provides a monolithic 1Tbit memory using 210 word-line layers. This represents an exercise in optimization with a 3.2Gbps read interface and 205Mbyte per second programming throughput. The component stores three bits per memory cell and achieves a density of 17Gbits per square millimeter.
A physical 8-plane architecture realizes read-latency of 40 microseconds and
high program throughput of 205Myte per second. A one-pulse-two-strobe technique reduces sensing time by 18 percent and contributes to the achievement of 205MB/s program throughput.
>300 layers
Researchers from Kioxia and long-time partner Western Digital are set to contribute Paper T7-1 “Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical silicon Channel in Ultra-High (> 300 Layers) 3D Flash Memory”
Metal-induced lateral crystallization allows 14micron-long ‘macaroni’ format channels to be formed in a vertical memory hole with more than 300 layers. The authors describe a recently developed nickel gettering technique. The 112 word line layered 3D NAND flash exhibits a greater than 40 percent read-noise reduction and a 10x improvement in channel conduction without degradation of memory cell reliability.
>400 layers
A paper from semiconductor manufacturing equipment supplier Tokyo Electron Ltd. helps chart a way to 3D-NAND flash with more than 400 layers, to double today’s commercial state of the art.
Paper T3-2 is “Beyond 10 micron Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers.” In this paper authors from Tokyo Electron Miyagi discuss a novel etching process for high aspect ratio hole patterning using cryogenic temperatures and a carbon-less chemistry. The authors have found that the hole can be etched through a wafer to 10-micron depth in a time of about 33 minutes. The etch profile is said to be excellent. The reduction of greenhouse gas emissions compared with other etch processes is 84 percent.
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