AMD teams for world’s largest FPGA-based adaptive SoC for emulation and prototyping
AMD has worked with arch-competitors Cadence, Siemens and Synopsys on the world’s largest FPGA for emulation and prototyping to support systems with up to 60 billion gates.
This is a safe claim as AMD, through the acquisition of Xilinx, is the only supplier of large FPGAs for these systems.
The VP1902 adaptive SoC provides 18.5M logic cells twice that of the previous Virtex UltraScale+ VU19P FPGA with four times the aggregate I/O bandwidth at 3.2 Gbit/s XPIOs at 36% lower latency says Manuel Uhm, Director of Versal Adaptive SoC Marketing for AMD Adaptive SoCs and FPGAs.
This is based on AMD Labs testing using an A6865 package to simulate the XPIO data rate performance of an AMD Versal Premium VP1902 device versus the published data rate of an AMD Virtex UltraScale+ VU19P FPGA.
The larger size and better connectivity is needed to emulate large system on chip and ASIC designs to run software before the chips tape out in the fab. Current systems are limited by the connectivity and and power consumption of the FPGA chips. This the first emulation FGPA chip to use the Versal architecture which uses chiplets in the package to boost the system performance.
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Enhanced debugging IP improves the device’s save-and-restore mechanism, resulting in up to 8X faster debug performance compared to the VU19P FPGA while a programmable network on chip (NoC) and hardened DDR memory controllers provide more resources. The NoC lets platform developers implement a control plane and route debug traffic—using the debugging IP—independently from the programmable logic. This frees up hundreds of look-up tables, saving routing resources for end users’ register-transfer level design.
The architecture also adds Scalar Engine accelerators that can execute complex applications that require support from an operating system that runs on the integrated ARM processing subsystem, making decisions within the device, and continuously reading back data for efficient debugging.
Related emulation system articles
- Synopsys looks to SoC digital twins with 30bn gates of FPGAs
- Pushing emulation beyond functional tests
- Cadence boosts its emulation and verification systems
- Mentor’s Veloce Apps push for more yield .
- Siemens EDA uses 2.5D packaging to boost verification
New features that support more efficient development on the VP1902 adaptive SoC include automated design closure assistance, interactive design tuning, remote multi-user real-time debugging, and enhanced back-end compilation, which enables end users to iterate IC designs faster.
The AMD Versal Premium VP1902 adaptive SoC will begin sampling in Q3 to those early access EDA customers with production expected in the first half of 2024.
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