Cadence collaborates with ARM on 5nm Neoverse datacentre chip designs
Cadence Design Systems has expanded its collaboration with ARM to support the latest Neoverse V1 and N2 cores for datacentre and 5G basetation chips.
ARM sees customers building chips with 128 N2 cores or 96 of the higher performance V1 cores on a single air-cooled chip. This gives higher performance with lower power by running a single thread on each core, rather than using multiple threads on a chip with less cores.
To build the chips, Cadence has provided 5nm and 7nm RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) to help customers such as Marvell optimize power, performance and area (PPA) goals and improve productivity. The Neoverse IP is also designed to support chiplets for high speed interfaces and stack memory chips.
The integrated digital full flow from Cadence has been proven on a 5nm, 4GHz Neoverse V1 implementation.
The RTL-to-GDS RAKs include the Genus Synthesis Solution, Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking and Conformal Low Power.
Cadence has also developed a full flow for verification. In particular, the Cadence System VIP solution has been enhanced with checkers, verification plans and traffic generators to verify Arm Neoverse-based SoC coherency, performance and ARM SystemReady compliance. All Cadence verification engines, including the Xcelium Logic Simulation, Palladium Z1 Emulation, Protium X1 Prototyping and JasperGold Formal Verification tools are used for ARM Neoverse-based SoCs.
“The modern infrastructure requires greater performance and power efficiency to manage next-generation high-performance computing and cloud-to-edge workloads,” said Chris Bergey, senior vice president and general manager, Infrastructure Line of Business at ARM. “By working with Cadence to optimize its digital and verification full flows for Arm Neoverse-based solutions, our customers can develop industry-leading products with optimal PPA.”
“Arm and Cadence have a long history of collaborating on Arm IP development, with the Neoverse V1 and Neoverse N2 platforms being the most recent example,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “By evaluating past customer successes with the Neoverse N1 platform, we’ve successfully optimized the Cadence digital and verification full flows to create high-frequency, low-power, high-quality server-class designs using Arm’s newest infrastructure platforms. With the new 5nm and 7nm RAKs and System VIP tools, our data centre and 5G infrastructure customers can rapidly deliver innovative silicon solutions on schedule.”
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