European supercomputer test chip tapes out

European supercomputer test chip tapes out

Technology News |
By Nick Flaherty

The EPAC 1.0 test chip is now ready to be sent to fabrication, It contains a number of accelerator cores some based on RISC-V instruction set architecture.

The EPI, a consortium of 28 partners from 10 countries, is set to receive €120 million from European Union taxpayers under the Horizon 2020 scheme to bolster its attempt to provide European independence in HPC chip technologies and HPC infrastructure.

The test chip contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics Technology Services (Barcelona, Spain) and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb.

Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and Forth, that provide a coherent view of the memory subsystem. The Stencil and Tensor accelerator (STX) was designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) by CEA LIST. These specialized accelerators are connected with very high-speed network on chip and SERDES technology from Extoll GmbH (Mannheim, Germany).

The test chip was finalized by Fraunhofer IIS for production by Globalfoundries using its 22FDX fully-depleted silicon-on-insulator (FDSOI) manufacturing process. It is due to be evaluated in an FPGA-based board being designed by Forth, E4 and the University of Zagreb.

The knowledge gained will be used to design a next-generation of EPAC accelerators and interfaces targeting 12nm manufacturing processes and below and adding a chiplet-style design and packaging approach, EPI said in a press release.

“It is a fully European design, driven by a vision of throughput-oriented computing and featuring characteristic that will result in high programmer productivity and achieve very high performance at low power and cost,” said Jesus Labarta, EPAC coordinator, in the same statement. “Although just an initial test chip, it can be a significant step forward in HPC but also for edge and embedded applications,” he added.

Norbert Schuhmann of Fraunhofer IIS said the accelerator IP cores are expected to run at clock frequencies of more than 1GHz and operate smoothly with memory accesses and data transport inside the chip and to the peripherals at rates above 200 Gbit/s.

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