First CXL 3.0 verification IP ships
Avery Design Systems has shipped its first verification IP for the latest version 3.0 of the Computer eXpress Link (CXL) specification, also launched today.
CXL is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. CXL 3.0 doubles the bandwidth of the interconnect with the same latency by using the next generation PCI Express PCIe 6.0 PHY for 64 GT/s transfers.
“We continue to evolve and enhance our solution as new versions of CXL emerge. By offering a VIP and supporting verification solution in support of CXL 3.0 for the first wave of CXL 3.0 designs we can enable leading developers of server processors, managed DRAM and storage class memory (SCM) buffers, switch/retimer, and IP companies to rapidly meet the growing needs for the CXL datacentre ecosystem in 2022 and beyond,” said Chris Browy, vice president sales/marketing of Avery.
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“Our collaboration with key ecosystem companies allows us to deliver best-in-class, robust CXL 3.0 VIP solutions that streamline the design and verification process and foster the rapid adoption of the CXL standard by the industry.”
Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe 6.0 and CXL 3.0 for CXL host, Type 1-3 devices, switches, and retimers.
The CXL 3.0 VIP also includes an additional CXL switch agent with fabric manager support as wellas support for the AMBA CHI on-chip bus to connect to CXL/PCIe via CXS.
Dynamic configuration of VIP supports legacy PCIe, CXL 3.0, 2.0 or CXL 1.1 including CXL device types 1-3 and includes realistic traffic arbitration among CXL.IO, CXL.Cache, CXL.Mem and CXL control packets as well as a unified user application data class for both pure PCIe and CXL traffic.
CXL VIP for CXL 3.0/2.0/1.1 is available today.
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