First CXL2.0 controller IP for datacentre chips

First CXL2.0 controller IP for datacentre chips

Technology News |
By Nick Flaherty

Synopsys IP for the latest PCI Express 5.0 standard has passed its compliance testing for integration into high performance datacentre chips using CXL2.0.

The IP enables early development of PCIe 5.0 system-on-chip (SoC) designs with higher interconnect speed to memory sub-systems using the CXL2.0 specification for cache coherenecy..

The PCIe 5.0 digital controllers and PHYs are the first IP to be listed on the 5.0 Integrators List and were tested with the Teladyne LeCroy Z516 Exerciser. The 5.0 version of the PCIe specification increased the data transfer speed and bandwidth capabilities to a maximum link speed of 32 GT/s offering up to 128 GB/s.

The Synopsys CXL 2.0 Controller IP is the first such controller to make the Integrator’s List for PCIe 5.0. The main advantage of using the CXL interface, which is based on PCIe 5.0 electrical specifications, is its cache coherency. While PCIe is ideal for applications with large data transfers, CXL is well suited for accelerators, co-processors, and other systems that share data from the same memory space.

While internal testing can be done to check cross-vendor functioning to a certain extent, passing PCIe compliance is a much more effective indication that the products’ interoperability with other vendors has been comprehensively validated by various industry leaders.

The process consists of two distinct testing categories: interoperability and Gold Suite tests. These are carried out at PCI-SIG Compliance Workshops and are the result of numerous development events conducted between PCI-SIG member engineers. The members produce a set of tests and specifications designed to gauge each product’s conformance to key specification parameters and ensure functioning with other devices.

Gold Suite testing is where parts of the PCIe specification that have been judged as key components for interoperability are tested. These include using a variety of electrical protocol tests and related equipment, such as bit error rate testers to assess the quality of signal transmissions and oscilloscopes to view and analyze devices’ electrical signals.

While it’s impossible to verify every parameter and permutation of the PCIe specification at a week-long event, these tests represent the accumulated learnings of several thousand of engineer hours to focus on those that most influence interoperability.

While passing one compliance workshop is sufficient to get on the PCI-SIG Integrators List, continuing to attend and test at multiple workshops help develop the compliance tests and allow vendors to fortify their product from the very early stages of the design process, ensuring all electrical, transactional, and configuration specs are covered early on.

The tests need to work with both the controllers and the physical layer IP. A PHY by itself cannot be controlled appropriately to go through all the different components of compliance testing.

Vendors who specialize in one or the other typically need to partner with other industry players to ensure end-to-end compliance.

Synopsys runs its IP in both add-in cards (Endpoint) and system (Root Port) configurations, providing a broad interoperability perspective within the industry. Since most systems rely on PCIe Root Port designs from a few large CPU vendors that typically utilize proprietary implementations and not open-standard IPs, testing with them as an add-in card (Endpoint) is absolutely essential.

However, the only way to test with the wider variety of PCIe Endpoint implementations used in add-in cards is with a system and its associated PCIe Root Port IP. Since most other IP vendors test only as add-in cards, customers of their Root Port IP will have to implement their own system before being able to evaluate interoperability with all those other implementations.


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