First on-die Power Delivery Network analyzer
Movellus has developed the industry’s first on-chip sensor for power delivery network (PDN) characterization and monitoring.
Power integrity is vital to the performance and efficiency of any system-on-chip (SoC), particularly for high power AI chips and chiplets. The Aeonic Insight PDN IQ sensor (above) can be placed anywhere data is required, typically in around ten or 20 locations, to provide nanosecond resolution of the power network. The sensors are programmable, with a 512 deep buffer. This can provide trigger data via the JTAG network or the APB bus.
This builds on the Aeonic voltage regulator IP Movellus introduced last year to manage the power of complex chips where power is a limiting factor. “Everything now is coming down to tokens per joule because we are hitting the wall on power delivery,” Vikram Karvat, chief operating officer at Movellus tells eeNews Europe.
“The visibility today is at the voltage regulator, so then how are you going to measure the power as it becomes integrated. This responds in microseconds but you need nanoseconds and fundamentally this means the voltage curves are extremely challenging to correlate.”
“For example we might measure a droop but depending on the workload you don’t know whether that’s in the worst case timing. This can translate into over margins with an excess of power or throttle the processing with under margins.”
The Aeonic Insight PDN IQ can be used for characterisation of the power performance of a chip, and for production testing, for example to provide data for ATE test systems. The sensors also be used to test the chips in the field, for example once they are installed in an AI datacentre.
“With hundreds of thousands of units in clusters, individual failures in a node in a sub-cluster impact the whole cluster. You can’t afford to restart a 6 to 8 month training run
“The PDN also isn’t just what’s on chip, there’s the voltage regulator and the test boards, so you have variances with different workloads. The worst case timing paths may not have been activated with scan testing, and you don’t have visibility
“This is fully digital IP we can place anywhere we think there is need to observe the PDN and integrate easily with the clock plane, sampling at a high clock speed typically 1GHz.”
“I would expect this would be put in of the order of tens of sensors,” he said. “Where we have early customer input this would be alongside sensitive interface such as the die to die, the HBM interface, and then into the cores. It could go into a cluster of two or four ARM cores, or for a large systolic array for an AI engine there could be multiple sensors, or multiple sensors for monitoring caches.”
The digital IP can be integrated into a chip design, and Movellus is also building a set of software APIs that will be published with libraries that will be easy to integrate into tools for programming the sensors and monitoring the data. This will enable the output of the sensors to be integrated with third-party analytics platforms. Silicon teams can feed telemetry data from the trace buffer and other registers available in the IP into an analytics stack to gain deeper insights into PDN behaviour.
Chips using the PDN are expected in 2027.
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