IAR supports 64bit RISC-V in development tool
IAR Systems in Sweden has added 64bit RISC-V core support with symmetric multiprocessing to its IAR Embedded Workbench
IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain in a single IDE, including integrated code analysis tools ensuring code quality. The optimization technology in IAR Embedded Workbench for RISC-V helps the application fit the required needs and optimize the utilization of on-board memory.
Version 3.10 of IAR Embedded Workbench for RISC-V supports RV64 RISC-V cores, including several RV64 devices from Andes, Codasip, Microchip, Nuclei and SiFive further extending the toolchain’s wide support for available RISC-V devices. In addition, symmetric multicore processing (SMP) is now supported, enabling high-performance debugging of multicore RISC-V devices.
Other IAR RISC-V articles
- IAR Systems, Codasip team for low-power RISC-V applications
- Functional safety tools certified on RISC-V
- RISC-V development tools add IEC 61508 and ISO 26262
“64bit support is an important milestone for our investment in the RISC-V technology and ecosystem,” said Anders Holmberg, CTO, IAR Systems. “RISC-V technology adoption and interest continues to grow, especially in the Asia Pacific region, and we are committed to stay in the forefront when it comes to professional development solutions for building high-quality embedded applications across all industries.”
Along with the Workbench, IAR provides build tools for RISC-V enabling modern and scalable build server topologies for continuous integration and development (CI/CD) pipelines as well as functional safety-certified editions of the toolchain.
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- IAR Systems and Secure Thingz add support for STM32 MCUs
- IAR Systems adds support for Renesas RE MCU family
- Fraunhofer zooms RISC-V into the functional safety zone
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