Intel muddies the data centre waters with IPU roadmap
Hot on the heels of its Gaudi2 AI accelerator, Intel has revealed its roadmap for its Infrastructure Processor Unit (IPU).
Intel used the term last year to launch custom programmable accelerators for data centre designs using the FPGA it acquired with Altera. It is planning to launch its second generation IPU, an ASIC called Mount Evans, and an FPGA version called Oak Springs Canyon. These were developed with Google Cloud.
These of course have nothing to do with the Intelligence Processing Unit (IPU) developed by GraphCore for AI acceleration in datacentres.
The Intel IPUs build on the network interface controllers from the FPGAs and hardware accelerated NVM storage interface scaled up from Intel’s shuttered Optane memory technology to emulate NVMe devices. The IPU also includes accelerators for cryptography and compression acceleration.
The third generation 400Gbit/s IPUs, code-named Mount Morgan and Hot Springs Canyon, are expected to ship to customers and partners in 2023 or 24, to be followed by 800Gbit/s devices in 2025/6.
- Intel finalises Altera acquisition
- Intel backs RISC-V for Nios FPGA processor
- Graphcore boosts AI performance to exascale with wafer on wafer technology
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