Intel taps Ashling for RISC-V development tools

Intel taps Ashling for RISC-V development tools

Business news |
By Nick Flaherty

Intel has teamed up with Ashling to provide development tools for its NIOS-V processor based on the open source RISC-V instruction set in FPGAs and ASICs.

The NIOS-V cores are included in v21.3 of the Quartus Prime tools for Intel’s FPGAs as the successor to the NIOS II soft core launched in 2004. Intel is starting with the V/m 32bit embedded microcontroller with a 5 stage execution unit and is planning a general purpose and ‘application class’ versions and as well as a 64bit version for Linux. As well as Linux, Intel already support the Micrium uC real time operating system (RTOS) and plans to support the Zephyr and FreeRTOS RTOS.

Working with Ashling provides a broad eco-system of tools with the RiscFree Eclipse-based IDE and unified debugger supporting both the 32bit and 64bit versions, says Hugh O’Keeffe, CEO of Ashling in a joint white paper. The company is also supplying tools for the latest MIPS RISC-V processor IP cores.

Intel plans to offer RISC-V as partner products manufactured on its process technology through the Intel Foundry Service, cores licensed as differentiated IP blocks, and as chiplets that make use of the Intel packaging and high speed chip-to-chip interface technology.

The RiscFree tools can be used for the soft core in Intel’s FPGA, and the hardened cores for the eASIC and full ASIC designs.

The two companies have worked together on the toolchains, with the RiscFree Project Manager and BuildManager tools supporting the application frameworks created by the Intel Quartus software. The NIOS V GCC compiler is fully integrated into the IDE with support for the newlib and picolibc runtime libraries using the NIOS V hardware abstraction layer (HAL) API for the hardware access.

RiscFree also provides debug awareness of realtime operating systems and multicore Linux kernels, and supports custom RISC-V instructions and extensions that can be used in the controller cores.;

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