Picocom samples its RISC-V OpenRAN chip
Picocom has received working samples of its multicore RISC-V PC802 chip for OpenRAN telecoms systems and is looking to raise additional funding.
The PC802 is a purpose-designed PHY chip built in a 12nm process for 5G NR/LTE small cell disaggregated and integrated RAN architectures that also includes support for 4G.
The chip has 3.5bn transistors and includes support for the Open RAN specifications with interfaces with a layer 2/3 stack via the SCF FAPI interface over PCIe. The PC802 supports seamless interfacing to Radio Units (O-RU) via the O-RAN Open Fronthaul (eCPRI) interface or directly to RFICs with a standardised JESD204B high-speed serial interface.
“We had the first samples back two weeks ago. After two days we sorted out the board problems and its gone spectacularly well. It has passed all the tests so we have working silicon,” said Pete Claydon, president of Picocom.
“OpenRAN is quite a hot topic and the community has been working with FPGAs and off the shelf processors which is fundamentally more costly. What the OpenRAN community needs is optimised silicon and that’s now in the market,” he said.
“The PC802 is optimised for OpenRAN with the Open FrontHaul protocol over 25G Ethernet built in so you can connect it directly to fibre and we do all the header processing on chip. The Small Cells Forum define FAPI for messaging between layer 1 and 2 and this is built into the software so we have two open interfaces at either end of our device and you only get that if you are designing something specifically for that purpose,” he said.
The chip has been designed over the last three years in Bristol, UK and China using an emulation system and high level C model.
“We have a Cadence Palladium box and that allows us to run the chip in about 1/1000th of real time,” he said. “That gives us a second of real time in 20 minutes of emulation and that has allowed us to run a lot of test cases and this gives us confidence in the design. We also have a C model of all the basic functions and that allows us to run all the protocols in real time with lower throughput and that allows us to connect to radios in real time. Having proved all the hardware of the chip, we are now bringing up the system software.”
The company has so far raised around $30m (€26m). “We are well engaged with investors and everyone has been waiting for the chip as a major landmark,” he said. “We can raise more money now and we are not seeing any barriers. I’ve been amazed by the traction we have in the market pre-silicon.”
Next: Production ramp
The company plans to ramp up production next year but has already had challenges with the packaging.
“We have orders now for samples and anticipating reasonable orders in Q3 2022 after qualification,” he said. “Our customers are in the US, China, Japan and Taiwan, but Europe, not so much. We are well engaged with a more limited number of prospects in Europe.”
The chip consumes around 4W in a radio unit or up to 10W on a PCI Express card, and the company also plans to supply a PCIe card with four PC802 chips.
“The area we have had issues is the package substrates. We did some quick-turn packages for 100 early samples as the lead times have been huge so we had to go to a specialist supplier. Now we are ordering ahead for packaging in Q3 for the flip chip with a pressed metal lid,” said Claydon. “The power depends on he use case. In the radio unit its about 4W but there are others where its about 10W on a PCIe card with a heatsink and forced air cooling.”
The use of the C model has allowed early integration with other OpenRAN systems.
“We have an integration with Radisys which has 4G and 5G functions which for private networks is pretty much essential and we are licensing separate software for 4G and 5G,” said Claydon.
The next chip design is well established. “Our next chip is not too far off,” said Claydon. “It’s at the RTL stage and we have a pipeline of products coming through. Now it’s about building an organisation around those products.”
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