Europe shows 2nm, quantum technologies at IEDM

November 29, 2021 // By Nick Flaherty
Europe shows 2nm, quantum technologies at IEDM
Backside routing for 2nm SRAM, a fully integrated GaN system on chip, silicon quantum processor and 3D chiplet routing are all papers from imec at the IEDM 2021 conference next month

Belgian research group imec has a strong presence at the 2021 IEEE International Electron Devices Meeting (IEDM) with 21 papers, making imec the biggest contributing organization at the conference.

The papers show progress in a variety of domains such as logic, memory, power device technology. More specifically, imec reports breakthroughs in monolithic GaN Power ICs, CMOS-compatible nano-scale domain wall devices, 3D SoC design, backside interconnects, IGZO-based DRAM cell architecture for 3D-DRAM memories and novel 2D device architectures for large-scale quantum computers. 

Using the back of a wafer for backside (BS) interconnect for signal routing in SRAM macro and logic at 2nm technology node can address the technology challenges of frontside (FS) BEOL routing congestion. Compared to the FS BEOL, the BS routing is very beneficial in improving performance of long interconnect signals.

A paper on 200 V GaN-on-SOI Smart Power Platform for Monolithic GaN Power ICs demonstrates a 200 V GaN-on-SOI smart power ICs platform developed on 200 mm substrates. Depletion-mode (d-mode) MIS-HEMTs and Gated-Edge-Termination Schottky barrier diodes (GET-SBDs) have been successfully integrated in an enhancement-mode (e-mode) HEMT technology baseline. A variety of low-voltage devices and passive components further support the GaN ICs platform.

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Domain wall (DW) motion offers a flexible design for novel computational schemes. Imec has demonstrated a full electrical operation of nanoscale DW devices, fabricated on 300 mm wafer hat could be used for logic.

The labs are also driving 3D integration of chiplets for System-on-Chip design methodology with a technique that reduces latency between blocks. In 3D-SoC, the system is automatically partitioned into separate chips that are concurrently designed & interconnected in the 3rd dimension with scaled pitches.

A fully 300-mm capacitorless DRAM cell using Indium gallium zinc oxide (IGZO) has retention over 1000s and endurance of over 1E11 cycles. The

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