Rambus, AIchip team on 4.0Gbit/s HBM2E memory interface for machine learning

Rambus, AIchip team on 4.0Gbit/s HBM2E memory interface for machine learning

Technology News |
By Nick Flaherty

Rambus achieved a record 4 Gbit/s performance for the latest HBM2E high bandwidth memory interface with a fully-integrated PHY and controller.

Combined with HBM2E DRAM from SK hynix operating at 3.6 Gbit/s provides 460 GBytes/s of bandwidth from a single HBM2E device. This meets the terabyte-scale bandwidth needs of accelerators for machine learning training and high-performance computing (HPC) applications.  

“With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world’s fastest HBM2E DRAM running at 3.6 Gbit/s from SK hynix,” said Uksong Kang, vice president of product planning at SK hynix. “In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available.”

The fully-integrated, production-ready Rambus HBM2E memory subsystem runs at 4.0 Gbit/s without PHY voltage overdrive. The IP was validated with SK hynix and Taiwanese ASIC house Alchip using TSMC’s N7 7nm process and CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technologies. Co-designing with the engineering team from Rambus, Alchip led the interposer and package substrate design and the 2.5D package and interposer reference design is part of the IP license.

“This advancement of Rambus and its partners, using TSMC’s advanced process and packaging technologies, is another important achievement of our ongoing collaboration with Rambus,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “We look forward to a continued partnership with Rambus to enable the highest performance in AI/ML and HPC applications.”

“Alchip brought a demonstrated track record of success in 7nm and 2.5D package design to this initiative,” said Johnny Shen, CEO of Alchip Technologies. “We’re extremely proud of our contributions to Rambus’ breakthrough achievement.”

“With silicon operation up to 4 Gbit/s, designers can future-proof their HBM2E implementations and can be confident of ample margin for 3.6 Gbit/s designs,” said Matthew Jones, senior director and general manager of IP cores at Rambus. “As part of every customer engagement, Rambus provides reference designs for the 2.5D package and interposer to ensure first-time right implementations for mission-critical AI/ML designs.”

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