Xilinx reveals FPGA & programmable SoC product plans for 16-nm silicon technology
There is a virtual blizzard of new and modified product names and brand identities to penetrate; the high-end FPGAs become UltraScale+; Zynq gains multi-core hard processors (“All-programmable MPSoC”); embedded memory options are UltraRAM; and a revised interconnect strategy is SmartConnect. This release predominantly gives details of device plans ahead of availability, setting out product plans for forthcoming quarters to enable designs to begin ahead of device delivery.
A fix on that pipeline is that Xilinx says that some of its 20nm devices are now starting to move to full production: however, some of the performance (particularly, performance-per-Watt) comparisons are made from the current 28-nm product direct to the planned 16-nm step. One other piece of branding of note is that the company refers to “3D-on-3D”. The first 3D alludes to the use of 3D transistors (that is, non-planar, or finFET); the second to its multi-die fabrication of its largest devices. This continues to use active devices side-by-side on a passive silicon interposer, often characterised as “2½D”.
Some of the application spaces that Xilinx is targeting with this generation include LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial IoT.
The announcement is of the 16nm UltraScale+ family of FPGAs, 3D ICs and MPSoCs, combining new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies. The UltraScale+ family also includes a new interconnect optimisation technology, SmartConnect. These devices extend Xilinx’s UltraScale portfolio – now spanning 20nm and 16nm FPGA, SoC and 3D IC devices – and gain a significant boost in performance/watt from TSMC’s 16FF+ FinFET 3D transistors.
With “optimisation at the system level” Xilinx says that the step to UltraScale+ delivers much more of an increment than does a traditional process node migration – providing 2–5X greater system level performance/watt over 28nm devices, more systems integration and intelligence, and the highest level of security and safety.
The UltraScale+ FPGA portfolio comprises Xilinx’s Kintex UltraScale+ FPGA and Virtex UltraScale+ FPGA and 3D IC families, while the Zynq UltraScale+ family includes the industry’s first all programmable MPSoCs.
While Xilinx’ programmable fabric has long had distributed RAM, the company says that many applications now need larger blocks; hence, its Memory Enhanced Programmable Devices with UltraRAM which “attacks one of the largest bottlenecks affecting FPGA- and SoC-based system performance and power” by enabling SRAM integration. The new technology can be leveraged to create high capacity on-chip memory for a variety of use cases – including deep packet and video buffering – providing predictable latency and performance. By integrating massive amounts of embedded memory very close to the associated processing engines, designers can achieve greater system performance/Watt and BOM cost reduction. UltraRAM scales up to 432 Mbits in a variety of configurations.
SmartConnect interconnect optimisation technology for FPGAs provides an additional 20-30% performance, area, and power advantages through intelligent system-wide interconnect optimisation. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking, and logic fabric, SmartConnect applies interconnect topology optimisations to match design-specific throughput and latency requirements while reducing interconnect logic area.
The new Zynq UltraScale+ MPSoCs include these FPGA technologies together with a broader range of embedded processor core options. Xilinx says that “the right engines for the right tasks” can deliver up to 5X system level performance/watt relative to previous alternatives. A 64-bit quad-core ARM Cortex-A53 processor, capable of hardware virtualisation, asymmetric processing, and full ARM TrustZone support, is paired with a dual-core ARM Cortex-R5 real-time processor for deterministic operation, ensuring responsiveness, high throughput, and low latency for the highest levels of safety and reliability. A separate security unit enables military-class security solutions such as secure boot, key and vault management, and anti-tamper capabilities—standard requirements for machine-to-machine communication and industrial IoT applications.
For complete graphics acceleration and video compression/decompression, the new device incorporates an ARM Mali-400MP dedicated graphics processor as well as a H.265 video codec unit, combined with support for Displayport, MIPI and HDMI. The video codec is an option; in the devices that have it, it is a hard block, but physically located in the FPGA fabric where immediate access to its is most likely to be needed. Finally, dedicated platform and power management unit (PMU) has been added that supports system monitoring, system management and dynamic power gating of each of the processing engines.
For the UltraScale+ families, first tape out and early access release of the design tools are scheduled for the second calendar quarter of 2015. First shipment of silicon is scheduled for the fourth calendar quarter of 2015.
Xilinx; www.xilinx.com/ultrascale
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