First SoC with CXL 2.0 as memory accelerator

November 17, 2021 // By Nick Flaherty
First SoC with CXL 2.0 as memory accelerator
Astera Labs Leo system on chip is the first to implement the CXL.mem standard for tiered memory for data centre servers

Astera Labs has developed the first chip to implement the latest CXL 2.0 memory interconnect standard.

The Leo Memory Accelerator Platform uses the Compute Express Link (CXL) 1.1/2.0 standard to connect pools of disaggregated memory and processors, AI accelerators and smart I/O devices. Leo overcomes processor memory bandwidth bottlenecks and capacity limitations while offering built-in fleet management and diagnostics for large scale enterprise and cloud server deployments.

“CXL is a true game changer for hyperscale data centres, enabling memory expansion and pooling capabilities to support a new era of data-centric and composable compute infrastructure,” said Jitendra Mohan, CEO of Astera labs. “We have developed the Leo SoC platform in lockstep with leading processor vendors, system OEMs, and strategic cloud customers to unleash the next generation of memory interconnect solutions.”

CXL is growing in adoption in the cloud, driven by the need for more memory and AI. The first CXL-enabled memory modules started shipping in May this year.

Leo is the industry’s first CXL SoC to implement the CXL.memory (CXL.mem) protocol, allowing a CPU to access and manage CXL-attached DRAM and persistent memory over PCI Express 5.0 lanes. This provides more efficient utilisation of centralized memory resources.

Astera has used its experience with CXL retimers to boost the overall memory bandwidth to 32 GT/s per lane and capacity up to 2TB with latency of , to provide server class reliability and availability for cloud scale operation. CXL 2.0 adds support for switching, persistent memory, and security as well as memory pooling support to maximize memory utilization, reducing or eliminating the need to over-provision memory.

“The introduction of CXL provides a critical capability to create a unified, coherent memory space between CPUs and accelerators, and this innovation will revolutionize how data centre server architectures will be built for years to come,” said Jim Pappas, Director of Technology Initiatives at Intel. “Astera Labs’ Leo CXL Memory Accelerator Platform is an important enabler for the Intel ecosystem to implement a shared memory space between hosts and attached-devices.”

“AMD recognizes the tremendous value that CXL brings to heterogeneous computing to meet the industry’s need for increased compute capacity and faster data processing through resource disaggregation,” said Michael Hall, director of customer compatibility, AMD. “Solutions like Astera Labs’ Leo Memory Accelerator Platform are critical to enable tighter coupling between AMD processors, accelerators and memory expansion.”

“To continue to enable the rapid growth of heterogeneous computing, we need to remove barriers such as the cost of scaling memory and highspeed interconnects across enterprise, hyperscaler, storage and accelerator applications,” said John DaCosta, senior director, strategic segments at ARM. “ARM sees CXL as a significant driver in this space, and Astera Labs’ new platform will help to address these needs in cloud and edge computing data centers using ARM-based technology.”

“Astera Labs has been a valuable member to the CXL Consortium contributing its expertise in enabling connectivity for heterogeneous compute architectures,” said Barry McAuliffe, CXL Consortium President. “We are pleased to see Astera Labs launch its first CXL memory expansion and pooling solution to support the rapidly expanding CXL ecosystem.”

www.AsteraLabs.com

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