BittWare has launched an FPGA card that can be programmed with the same interface as a CPU and GPU.
The IA-840F is BIttWare’s first card to use Intel’s Agilex FPGA card for data centre, networking and edge compute workloads. This will use Intel’s oneAPI, which enables an abstracted development flow for dramatically simplified code re-use across multiple architectures from CPUs and GPUs. The ’golden’ version of oneAPI is set to be launched in December.
BittWare maximized I/O features using the Agilex chip’s unique tiling architecture with dual QSFP-DDs (4× 100G), PCIe Gen4 x16, and three MCIO expansion ports for a wide range of applications.
“Modern data centre workloads are incredibly diverse requiring customers to implement a mix of scalar, vector, matrix and spatial architectures,” said Craig Petrie, vice president of marketing for BittWare, which is part of Molex. “The IA-840F ensures that customers can quickly and easily exploit the advanced features of the Intel Agilex FPGA. For those customers who prefer to develop FPGA applications at an abstracted level, we are including support for oneAPI. This new unified software programming environment allows customers to program the Agilex FPGA from a single code base with native high-level language performance across architectures.”
The HDL developer toolkit includes the API, PCIe drivers, application example designs and diagnostic self-test with a Board Management Controller (BMC) and a choice of thermal options including passive, active or liquid cooling.
To streamline cross-architecture development, oneAPI includes a direct programming language, Data Parallel C++, and a set of libraries for API-based programming. Data Parallel C++ is based on C++ and incorporates SYCL from the Khronos Group. This dramatically simplifies code re-use across multiple architectures while facilitating custom tuning for accelerators.
“Intel Agilex FPGAs and cross platform tools including the oneAPI toolkit are leading the way to enable easier access to these newest FPGAs and their tremendous capabilities - including eASIC integration, HBM integration, BFLOAT16, optimized tensor compute