Qualcomm has moved into a new 4,600m 2 centre at Penrose Dock in Cork in October and is recruiting for ASIC designers working in digital, analog, machine learning, automotive, CAD, software engineering and system validation.
It already has staff in the region. Engineers Michele Chilla and Leonardo Gobbi at the centre ealier this month won the best paper award at the DVCon Europe conference. They are looking at how the same complex Multi-Clock Digital IP System design is impacted by different RTL design strategies for the Clock Control Unit (CCU).
The paper, Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level, looked at a real example of a digital wireless front end with over 300k flip-flops and all design features such as bus infrastructure linking complex internal cores. The RTL also included design for test (DFT) logic used to test all the faults of the chip on silicon.
The facilities of specially-purposed labs to support security and validation work, said Ajay Bawale, vice president of engineering at Qualcomm Technologies
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