Intel outlined its path toward more than 10x interconnect density improvement in packaging with hybrid bonding, 30 to 50 percent area improvement in transistor scaling, and new quantum computing technologies at the IEEE International Electron Devices Meeting (IEDM) last month,
“At Intel, the research and innovation necessary for advancing Moore’s Law never stops. Our Components Research Group is sharing key research breakthroughs at IEDM 2021 in bringing revolutionary process and packaging technologies to meet the insatiable demand for powerful computing that our industry and society depend on. This is the result of our best scientists’ and engineers’ tireless work. They continue to be at the forefront of innovations for continuing Moore’s Law,” said Robert Chau, Intel Senior Fellow and general manager of Components Research
The Components Research Group is working in three key areas: scaling technologies for delivering more transistors; new silicon capabilities for power and memory gains; and exploration of new concepts in physics to revolutionize the way the world does computing.
Many of Intl's current semiconductor products started with the work of Component Research, including strained silicon, Hi-K metal gates, FinFET transistors, RibbonFET, and packaging including EMIB and Foveros Direct.
Researchers at the company have outlined solutions for the design, process, and assembly challenges of hybrid bonding interconnect, seeing a way to a 10x interconnect density improvement in packaging. Back in July, Intel announced plans to introduce Foveros Direct, enabling sub-10-micron bump pitches, providing an order of magnitude increase in the interconnect density for 3D stacking. To enable the ecosystem to gain benefits of advanced packaging, Intel is also calling for the establishment of new industry standards and testing procedures to enable a hybrid bonding chiplet ecosystem.
Looking beyond its gate-all-around RibbonFET, Intel is developing an approach to stacking multiple CMOS) transistors that aims to achieve a maximized 30 to 50 percent logic scaling improvement for the continued advancement of Moore’s Law by fitting more transistors per square millimetre.
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