IP blocks boost 5G NR performance

February 18, 2021 //By Nick Flaherty
IP blocks boost 5G NR performance
AccelerComm’s fully integrated PUSCH decoder boosts 5G NR in MIMO wireless channels where performance is critical

UK IP developer AccelerComm has developed physical layer blocks for the latest 5G NR New Radio systems.

The complete 5G NR PUSCH (Physical Uplink Shared Channel) Decoder and PDSCH (Physical Downlink Shared Channel) Encoder is aimed at systems using multiple MIMO antennas to boost the

The IP blocks build on the company’s carrier-grade portfolio of channel coding and modulation/demodulation IP that is used in OpenRAN designs. This provides the error correction decoding that is required to overcome the effects of noise, interference and poor signal strength.

The PUSCH Decoder integrates additional 3GPP physical layer functions together with its high-performance LDPC decoders, to create a 3GPP-compliant IP package that can be quickly integrated and optimized for use in custom silicon ASICs and programmable FPGAs. The flexible architecture means that it can be customized depending on an operator’s service requirements, resulting in optimal performance, power, and silicon area, tailored to their specific needs.

The IP blocks complete the link between the LDPC decoder and the MIMO detector for industrial IOT systems as well as low latency 5G control of driverless cars and drones.  

“Spectrum is a scarce resource, and is the key asset owned by mobile operators, so it is critical that they maximize its use - every dB counts,” said Robert Barnes, VP Sales & Marketing of AccelerComm, a spinout of Southampton University. “This product builds on the existing AccelerComm IP portfolio to enable operators to deliver on the high-performance, low-latency promise of 5G using their existing spectrum and cloud RAN infrastructure.”

The gNodeB uplink stack in the PUSCH decoder includes the LDPC decoder with transport block wrapper, polar decoder, demultiplexer, descrambler and QAM demodulator. The PDSCH encoder has the LDPC encoder with transport block wrapper, scrambler, and QAM modulator

The specification is as defined in Sections 6.2 and 7.2 of 3GPP document TS 38.212, as well as Sections 6.3.1.1, 6.3.1.2, 7.3.1.1 and 7.3.1.2 of TS 38.211.  

www.accelercomm.com

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