ISSCC sees 3nm process, compute-in-memory : Page 3 of 4

December 21, 2020 // By Peter Clarke
3nm GAA process, compute-in-memory among highlights of ISSCC 2021
The International Solid-State Circuits Conference (ISSCC) in February 2021 will include details of 3nm technology and compute-in-memory for AI

Session 16 is one of a number of sessions that includes papers on compute-in-memory (also 15 and 29). This topic is well represented at the upcoming ISSCC and is something TSMC is clearly pushing hard.

Paper 16.1 – A 22nm 4Mbit 8bit-precision ReRAM computing-in-memory Macro with 11.91 to 195.7TOPS/W for tiny AI edge devices – is more academic with the principal authors coming from National Tsing Hua University, Hsinchu, Taiwan, but with TSMC well represented in the authoring team (see TSMC offers 22nm RRAM, taking MRAM on to 16nm).

But Paper 16.3 – A 28nm 384kbit 6T-SRAM computation-in-memory Macro with 8bit of Precision for AI edge chips – is an all TSMC paper. Meanwhile Intel has an embedded DRAM compute-in-memory paper in the same session (16.2) and TSMC has a paper on an SRAM block capable of 89TOPS/W and 16.3TOPS per square millimeter (16.4).

Session 24 is on advanced embedded memories and most notable here is Samsung's paper on its 3nm gate-all-round (GAA) manufacturing process. Paper 24.3 is A 3nm gate-all-around SRAM: featuring an adaptive dual-BL and an adaptive cell-power assist circuit.

Paper 24.4 from TSMC fills in some more detail of that foundry's 5nm manufacturing process offering with A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kbit standard-cell-based two-port register file with a 16T bitcell with no half-selection issue.

Paper 24.2 is nominally from Chinese academics at the Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, Zhejiang Lab, Hangzhou and Fudan University, Shanghai. The title is A 14nm-FinFET 1Mbit embedded 1T1R RRAM with a 0.022 square micron cell size using self-adaptive delayed termination and multicell reference. This gives rise to the thought that his may well represent part of the leading-edge at Chinese foundry SMIC.

Session 30 is nominally about non-volatile memory but in fact portrays the start-of-the-art in 3D-NAND with papers from SK Hynix (176 layers), Intel (144 layers), Samsung (160+) and Kioxia/Western Digital (170+ layers).

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