RISC-V reference simulator adds vector support

October 15, 2020 //By Nick Flaherty
Open source RISC-V reference simulator adds vector support
The open source riscvOVPsim RISC-V reference simulator and model from Imperas adds a test suite for the latest Vector Instruction Extensions

Imperas Software has updated and extended its reference simulator for RISC-V vector instructions and now supports coverage driven verification analysis.

The base version of riscvOVPsim is available for free from a new GitHub site, while an enhanced version including an extensive RISC-V vector test suite also freely available for commercial use from Open Virtual Platforms (see links below).

The upcoming ratification of the RISC-V Vector instruction extension offers system designers broad flexibility to configure vector engines to support complex arithmetic operations required for applications involving linear algebra, such High-Performance Computing and machine learning applications. With these latest enhancements to riscvOVPsim, software developers and system architects can start to explore RISC-V based solutions, while Design Verification (DV) Engineers can configure the models for test benches and test frameworks with coverage analysis.

The riscvOVPsim simulator includes an envelope model that supports all the RISC-V ratified specification options, which can be easily configured to match targeted processor features as a key step in setting up a verification test bench. riscvOVPsim has also been updated with coverage features that easily and efficiently support instruction functional coverage-based verification flows.

Imperas launched riscvOVPsim to support the RISC-V International compliance working group in 2018 and it has become widely adopted by both open source and commercial processor development teams looking for a dependable RISC-V reference model that can be easily configured and is the key reference within their compliance, directed and random test generation environments and frameworks.

The Imperas support for the RISC-V vector instruction extension also includes a new architectural validation test suite which features detailed instruction tests for a base vector engine configured as RV32GCV with elen:32, vlen:256, slen:256. The vector suite is built by the Imperas directed test generator and includes over 3 million instructions in 5-7,000 test files (depending on suite configuration), with full source, assertions, and reference signatures.

Next: RISC-V test coverage and links


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