Ashling tools for RISC-V space processor
Ashling is to provide its RiscFree Toolchain for software development support for the NOEL-V fault tolerant RISC-V space processors developed by CAES.
NOEL-V is a synthesizable VHDL processor model based on the open RISC-V architecture targeting mission critical electronics for aerospace and defence industries. Seven different configurations are now available from CAES in Sweden, ranging from a compact 32-bit version to a 64-bit high performance version. NOEL-V complements the LEON line of processors and is suitable for fault and radiation-tolerant FPGAs and ASIC designs for space and satellite applications.
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RiscFree is Ashling’s Integrated Development Environment (IDE) including a Compiler and Debugger and provides software development and debug support for NOEL-V. Since its introduction, Ashling’s RiscFree toolchain has been steadily building market share within the embedded tools market and is particularly strong in the RISC-V market, including MIPS, Intel and NXP cores that are under development.
“We are excited to partner with Ashling and have their RiscFree toolchain support our NOEL-V processors. CAES’ customers will benefit from our expanding development tools ecosystem as it will help expedite time to market,” said Mike Elias, Senior Vice President and General Manager Space Division, CAES.
“We are pleased to announce our support for CAES’ recently announced NOEL-V processor and that our RiscFree is now part of CAES’ eco-system of development and debug. We believe RiscFree support will offer the geospatial industry a leading Toolchain which will help in speeding up the deployment of any NOEL-V processor powered solutions.” said Hugh O’Keeffe, CEO of Ashling.
The RiscFree toolchain support for CAES’ NOEL-V processor includes Project Manager and Build Manager including Make and CMake support as well as Source-code Creation and Navigation support and a GCC toolchain fully integrated into the RiscFree IDE with support for newlib run-time library, run-time debug and debugger register V=view support for peripheral and CSR Registers.
The RTOS Debugger supports FreeRTOS Task and Queue Views and custom instruction support including additions to the standard RISC-V ISA. A real time trace feature is planned.
“The collaboration between Ashling and CAES on RISC-V is an example of progress made within the RISC-V community to support global adoption and proliferation of RISC-V.” said Calista Redmond, CEO, RISC-V International. “Together, the ecosystem is growing through IP and Toolchain providers working closely together.”
www.ashling.com/ashling-riscv/; www.caes.com/gaisler
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