European processor project shows shift to RISC-V

Technology News | December 23, 2021

By Nick Flaherty

The European Processor Initiative (EPI) has successfully completed its first three-year phase, delivering multicore chip designs for supercomputers and automotive

The project highlights a shift away from ARM to RISC-V iin the Rhea general-purpose processor, a RISC-V accelerator proof of concept and embedded high-performance microcontroller for automotive applications.

The project has 28 partners from 10 European countries aiming to make the EU achieve independence in high-performance computing (HPC) chip technologies.

The successful completion of the first phase, SGA1, paves the way for the second instalment of the project, which kicks off in January 2022.

The initial design of the General-Purpose Processor (GPP), called Rhea, had 72 ARM Zeus processors described to the Linley Conference.

French Supercomputer maker Atos is the lead partner of the General-Purpose Processor (GPP) stream, working with SiPearl. They defined the architectural specifications of Rhea, which now has 29 cores using the RISC-V open instruction set architecture and is at the RTL level in emulation, rathe than an implementation in silicon. The design is intended for use in a supercomputer design in 2023.

“With 29 RISC-V cores, the Arm Neoverse V1 architecture used by SiPearl to design Rhea will offer an effective, scalable and customisable solution for HPC applications,” said the project. “Architectural decisions were taken following a co-design methodology and by analysing the performance of advanced intellectual property (IP) blocks. A scalable network-on-chip (NoC) to enable high-frequency, high-bandwidth data transfers between cores, accelerators, input / output (IO) and shared memory resources was also optimised by SiPearl.”

“We are proud of our success in designing a powerful GPP leveraging cutting edge technologies and IPs built and deployed exclusively by European universities and industrial leaders. We are confident that we will soon demonstrate the instrumental role of this GPP in enabling a European exascale computing machine, the next breakthrough in the HPC domain the world is expecting,” said Stream Leader Emmanuel Ego at Atos.

“With the release of the Rhea processor, we will all contribute to ensure European sovereignty in HPC applications such as personalised medicine, climate modelling, and energy management.” – said Philippe Notton, founder and CEO of SiPearl.

Next: HBM2E memory architecture

Memory controllers are one of the most critical IPs when it comes to GPP performance. To help evaluate architectural choices, CEA developed a complete simulation platform with specific instrumentations to analyse controller efficiency in driving the high-bandwidth HBM2E memories. The platform allows efficient analysis of the memory device interface thanks to the decoding and tracking of all memory commands and data. The HBM2E subsystem was simulated with multiple random and directive patterns targeting different traffic shapes and involving all the controller features in maintaining the HBM2E efficiency.

A number of state-of-the-art embedded security features and key technologies were also designed in this stream. These include the standalone Security Management System (SMS) security IP developed by ProvenRun, providing advanced, common-criteria certified, sovereign security IP for HPC and edge processors.

The University of Pisa contributed a set of crypto IPs, called “Crypto Tile”, integrated in the Rhea GPP by SiPearl. This provides a hardware security module with full security services for high-end symmetric (AES with nine cipher modes), asymmetric (ECC, ECDSA, ECIES, ECDH) and hashing (SHA2/SHA3) cryptography, delivering several orders of magnitude of increased throughput and decreased energy cost as compared to a software solution.

The Crypto Tile also includes secure key storage and secure IP configuration, side-channel attack protection, on-chip true random number generation (TRNG), support of Linux kernel drivers, extreme key lengths for maximum security levels and high speed en(de)cryption throughput thanks to AXI4-based interface towards DMA and Arm or RISC-V programmable cores. Post-quantum cryptographic support is also provided thanks to real-time implementation of Lattice algorithms such as Crystals Kyber and Dilithium.

Next: RISC-V accelerators

The European Processor Accelerator (EPAC) test chip proof of concept uses open-source instruction-set architectures (ISAs) ensures freedom from proprietary licences and export restrictions, contributing to the expansion of the RISC-V ecosystem and adding to the LLVM compiler database.

The EPAC systems and FPGA software development vehicles make full use of the Linux operating system and contribute to the community with patches, device drivers, and additional functionality to popular open-source HPC software packages such as OpenMP and MPI. Furthermore, parts of the hardware such as the STX (stencil/tensor accelerator) were developed using a permissively licensed open-source approach around the PULP platform.

“The accelerator stream in EPI has emphatically proven that the RISC-V vector approach has the potential to transform the HPC sector, with designed-in-Europe architectures capable of delivering high performance on a low energy budget,” commented Stream Leader Jesús Labarta (Barcelona Supercomputing Center). “The work also epitomizes European traditions of open science and collaboration. Partners across Europe have joined forces to create something that no single organization could have achieved by itself. By working with open-source technologies and projects, the EPAC stream has helped expand the RISC-V ecosystem, making this technology viable for an increasing number of applications in the future.”

The EPAC vector processing unit (VPU), design by BSC and UNIZG, shows the use of RISC-V long-vector architectures for high-performance computing is a viable approach, delivering high performance on a low energy budget, and that it can be scaled up in future.

The vector unit is driven by Semidynamics’ vector-specialised Avispado RISC-V core and Gazzillion Misses technology for energy-efficient processing.

The dedicated and flexible RISC-V based many-core stencil and tensor accelerator (STX), designed by ETH Zurich and Fraunhofer, leverages stencil processing units to offer exceptional energy efficiency and programmability for machine-learning and stencil workloads.

Meanwhile, the variable precision accelerator (VRP), designed by CEA, enhances efficiency and reliability for scientific high-performance computing applications such as multiphysics simulations.

The EPAC test chip also includes multiple distributed banks of shared L2 cache and coherence home nodes (L2HN) designed by FORTH and CHALMERS and optimised for the high-bandwidth requirements of the vector processing units while offering a coherent view of the memory system that facilitates multi-core programmability.

All the processing units and the shared L2HN banks are connected via a high-speed NoC in a modular manner that permits the system to scale up. The test chip also includes advanced SERDES technology for very high-bandwidth off-chip and cross-chip communication. Both the NoC and SERDES were designed by Extoll.

The PCB (daughter board) to enable the testing of the EPAC Test Chip was designed and developed by E4 Computer Engineering.

Next: Automotive microcontroller

Coordinated by Infineon, a leader in automotive microcontrollers, the Automotive Stream has paved the way towards road-capable autonomous cars, thanks to the proof of concept for an innovative embedded high-performance compute (eHPC) platform and associated software development kit (SDK). This platform, in combination with a downsized, vehicle-tailored, general-purpose processor, meets the increasing demand for computing power in future cars in a cost-efficient, economically viable and functionally safe way.

“Overall, the achievements are evidence of collaboration, synergies and the team spirit which characterised the research work in the automotive stream”, – said Stream Leader Knut Hufeld (Infineon). “With its focus on cost-effective, safe and certified automotive solutions, it can be seen as a driving belt for the overall profitability of European processors in the field of HPC.”

The main achievement was demonstrated in a road-approved BMW X5 car to show the proof of concept for a pioneering eHPC Microcontroller Unit (eHPC MCU) which is integrated in a specially designed flexible modular computing platform (MCP) together with several EPI technology IPs. Numerous test drives were performed to collect data and evaluate test scenarios involving parameters of autonomous driving.

Among other features, the platform includes AI-supported integrated cameras and Elektrobit radar imaging analysis software, with integrated preparation for use of EPI accelerators in the system. It is the result of a close cooperation among the 16 partners in Stream4 aiming to fulfil its objectives of specifying a suitable eHPC Platform, define its architecture and develop the necessary software development kit (SDK).

Infineon also expanded the automotive microcontroller in terms of its architecture and performance ability so that it can act as master and control one or several accelerators. Relevant aspects were safety, security, fall back or redundancy for reduced application, with regard to the top Automotive Safety Integrity Level D (ASIL D) at system level, which is required for autonomous driving applications.

The platform is scalable and open for further technologies with slots for future automotive versions of the EPI general purpose processor, the EPAC RISC-V based accelerator as well as the Kalray Massively Parallel Processor Array (MPPA) accelerator tile for eHPC, developed as an IP in the Stream 2.

Test runs reveal that EPI now has specific technologies suitable for autonomous driving up to at least level 4.

In addition to the hardware platform, this stream also included the development of a complete software ecosystem, based to a large extent on software products by automotive software specialist Elektrobit. This area also comprises the automotive eHPC platform software stack, including the classic automotive open operating system architecture (AUTOSAR) development for Auto eHPC MCUs, and the adaptive AUTOSAR development for HPC GPPs and the L4Re hypervisor (virtualisation) that are crucial for automotive applications.

A specific concept was jointly created for a software lockstep, thus contributing to an overall EPI safety concept.

After this three-year initial phase, the results and findings will be continued in further projects.

“I’m proud of the outstanding results achieved by EPI teams after only three years of cooperation, paving the way towards Europe’s technological sovereignty. I’m particularly impressed we delivered our objectives on time with a limited budget, despite the unprecedented working conditions due to the terrible COVID-19 pandemic. This has created favourable conditions for the launch of the next phase and its successful delivery of the European processors and accelerators for the EUPEX (EUropean Pilot for Exascale) and TEP (The European Pilot) projects, the precursors to European exascale systems,” said Eric Monchalin (Atos), chairman of the EPI Board.

www.european-processor-initiative.eu/

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