Round 6 opens for Tiny Tapeout low cost ASICs
Cette publication existe aussi en Français
Low cost ASIC project Tiny Tapeout 6 is open for submissions, adding power gating for all designs, mixed signal support and analog pins.
Tiny Tapeout 6 has the same space, IOs and speed as the previous Tiny Tapeout 5, but the power gating opens up other design flows and submissions close on the 19th of April. The project combines hundreds of ASIC designs from researchers and developers on a single chip on a 130nm process run at Skywater that is then mounted on a board.
“Now that all designs are power gated, we’re accepting analog, mixed signal and submissions made with other flows or proprietary tools. As long as your design passes the Sky130 DRC rules, you’re in,” said Matt Venn, the organiser of the project. “If you want analog IO pins, the price starts from $40 each, and your design needs to use a minimum of 2 tiles. The analog mux is still in development and we plan to accept designs needing analog IO pins by early March.”
The results of the designs on a multiproject wafer run are expected back by October 2024 and ship to designers by December 2024. However the Covid-19 pandemic and low cost runs have meant that the TT02 projects have only just started shipping after testing.
The price of the multi-project wafer has also increased.
“When we first came up with the idea and pricing structure for TinyTapeout, the Efabless chipIgnite service provided 300 WLCSP chips for $10,000. Shortly after, the package changed to the more expensive QFN type, with the quantity reduced to 100,” said Venn.
“With the chips tripling in price, we’ve had to raise the price of the hardware to keep the business sustainable. The good news is that Efabless are still sponsoring us, so the first 100 submissions from individuals are only increasing by $50, to $150 for 1 tile, the ASIC and the demo board.
For businesses, universities, and individuals after those first 100 are sold, the new price is $300 for 1 tile, the ASIC and the demo board. If you need more space, extra tiles remain at $50,” he said.
There were 174 submissions for the recent TT05 project, using 75% of the available space and up from 160 for TT02. Designs on TT05 include a Linux-capable RISC-V processor, a field programmable neural array, a wavetable sound generator and a metastability experiment.
There is a new interactive chip map on the various projects here.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
