ARM splits its Neoverse datacentre server chip designs: Page 2 of 2

September 22, 2020 // By Nick Flaherty
ARM has split its Neoverse datacentre processors into separate lines for high performance and for scaling in existing racks and for edge AI.
ARM has split its Neoverse datacentre processors into separate lines for high performance vector processing and for scaling in existing racks and for edge AI.

can host more customers per rack and the customer gets better performance per core, he says. This could have up to 192 cores in a chip with a thermal profile (TDP) of 350W in teh data centre, or smaller core counts for edge and network applications.

“There’s a powerful story for 5G and edge computing where there are even more constraints on power. The defining characteristic is an equal focus on performance, power and area, whether that’s a 250W cloud SoC or 20W 5G basestation SoC,” he said.

V1 would have less cores but optimised for 40 percent higher performance than N2. “What we see is customers have a TDP to optimise around, going from air cooling to liquid cooling have different cost profiles so really it’s about the balance of TDP and computing performance, which is the thing with V1 vs N2. That kind of customisation is really interesting to the ecosystem,” said Bergey. “About 36 cores of V1 would be the high end of cooling.”

The IP will be launched later this year with more technical details on the architectures, and designs are progressing on TSMC 7nm and 5nm processes.

www.arm.com

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