EDA flow cuts ASIC modelling time from months to days

August 10, 2021 // By Nick Flaherty
EDA flow cuts ASIC modelling time from months to days
UK chip designer Sondrel has created a customised flow to cut the time it takes to model a chip.

Sondrel has developed a wrapper for ARM and Synopsys chip design tools to provide detailed architectural modelling provides reasonable estimates of the performance, power, memory resources, and the NoC (Network on Chip) configuration that will be required along with an indicative size of the die and what it is likely to cost.

With this information in just a few days, a customer can decide whether to proceed with a semi-custom ASIC chip design, if it needs to be adjusted or even cancelled.

“In the rapidly moving world of electronic systems where time to market is critical and chip designs can cost millions, we are always developing new ways to give our customers huge advantages in this race,” said Graham Curren, CEO and founder of Sondrel.

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“This enhanced architectural modelling is just one of many innovations that our extensive internal R&D programme has created for our turnkey service that enable us to rapidly provide customers with all the information that they need at the start of a project to understand all its aspects right through to cost per packaged, tested die,” he said. “We believe that we are unique in being able to provide such comprehensive information for architecting complex designs and at a level of detail and speed that our rivals cannot match. And, if we can use this with one of our predefined IP platforms for the customer’s design, we can reduce time, risk and costs even more dramatically.” 

Modelling tools are available as standard items but Sondrel has combined these in a custom flow to add a framework with a much greater number of settings that can be tweaked by the chip architect working on the project.

This is added using hooks into the vendor’s software that are provided for this very purpose. Typically, users create customisation wrappers that are specific to the designs that they work on if not already present in a library of an ever-growing number of such wrappers. However, because Sondrel works on a wide variety of projects for customers, it has defined a methodology and flows that are broader in scope so that they can be used for almost any architectural exploration project.

The biggest benefit of the modelling flow is to cut the time it takes to create a model and run simulations. This allows Sondrel to provide customers with data on the likely performance of a proposed ASIC in a matter of few days to determine if the architecture proposed gives an appropriate set of numbers. If not, it is very easy and quick to run variants of the model simply by changing the settings of the existing model.

Running each variation takes anywhere between a few minutes to an hour, so the whole process of model creation and running variants can still be done in the same timeframe.

Otherwise static spreadsheet modelling can take weeks for each variant, taking months to explore the different options.

www.sondrel.com

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