Sondrel semi-custom 4TOPS AI design

May 10, 2021 // By Nick Flaherty
Sondrel's semi-custom 4TOPS design boosts AI chips
Sondrel’s four-core SFA 300 design can be combined via the PCIe interface to scale performance for data centre applications

UK chip design house Sondrel has launched a quad-core semi-custom chip design for high performance data processing including AI or cryptocurrency mining.

Each SFA 300 reference design has four CPU clusters and several SFA 300s can be synchronised via a PCIe interface. Accelerator blocks and/or custom logic can be added for more performance and to reduce the overall power consumption.

The design is aimed at applications such as 8K video, AI, facial recognition for surveillance, smart factories, blockchain servers and medical data analysis.

“An ASIC with four CPU clusters is complex to design,” said Rowan Naylor, a Principal Engineering Consultant at Sondrel. “Moving data around the chip without bottlenecks needs a Network on Chip, a multi-width data path, internal RAM scaled and distributed across the design for optimal performance, and data conflict arbitration. Plus, there are the data security aspects in the Ar®-based security subsystem such as activity/intrusion detection. All this is already in the SFA 300 IP platform, so all that has to be done is integrating in the customer’s IP which cuts down the design time and costs by up to 30 percent.”

The SFA 300 is a framework where different ARM cores can be used to suit the processing power need by each of the four channels of the chip because the interconnects on and off the CPUs are standardised. This standardisation of interconnects on the boundaries of IP blocks and the rest of chip enables most other IP blocks such as memory to be also exchanged as required. Typical performance figures are 4 TOPS (Tera Operations Per Second) for each channel for AI and 400 GOPS (Giga Operations Per Second) for each channel for DSP.  

If the processing power required is greater than can be achieved by upgrading the processors, then several chips can be linked together to form a cluster to achieve the required processing power.

“This


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