IAR Systems, Codasip team for low-power RISC-V applications

December 01, 2021 // By Nick Flaherty
IAR Systems, Codasip team for low-power RISC-V applications
IAR’s Embedded Workbench for RISC-V now supports Codasip’s L30 and L50 low power embedded processor cores

IAR Systems is working with processor core and tool developer Codasip on tools for low-power embedded applications based on RISC-V.

Version 2.11 of the IAR Embedded Workbench for RISC-V now supports the L30 and L50 energy-efficient low-power embedded processor cores from Codasip. These cores are fully customizable and adaptable to the unique needs of a project, which requires more detailed integration with the development tools.

IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain integrated in one single IDE.

“Codasip L30 and L50 RISC-V processors are fully compliant with RISC-V specification allowing customers to choose from a variety of compilation and debug solutions,” said Zdeněk Přikryl, Chief Technology Officer, Codasip. “IAR Systems is a market leader in the embedded space and our processors work flawlessly with IAR Embedded Workbench."

“The Codasip L30 and L50 are powerful additions to the embedded RISC-V ecosystem,” said Anders Holmberg, Chief Technology Officer, IAR Systems. “We are committed to supporting both new and existing technology partners, as well as customers in making the most out of their investments in RISC-V by continuously expanding our RISC-V product portfolio."

www.iar.com/riscv; www.codasip.com.

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