ARM customers have successfully taped out mobile system on chip designs at 5nm using its Cortex-X2, Cortex-A710, and Cortex-A510 CPUs, Mali-G710 GPU and the DynamIQ Shared Unit-110.
As part of a collaboration, Cadence Design Systems has fine-tuned its digital and verification full flows on 5nm and 7nm process technologies to support the ARMv9 architecture with RTL-to-GDS digital flow Rapid Adoption Kits (RAKs). The move is significant as the majority of the ARMv9 focus has been on large chips for the datacentre using the Neoverse architecture. Synsopsys tools are also taking designs to 3nm.
The Cadence digital flow and corresponding 5nm and 7nm RAKs for the development of ARMv9 mobile SoCs include the Modus DFT Software Solution, Genus Synthesis Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking and Conformal Low Power.
The Cadence iSpatial technology provides an integrated, predictable implementation flow so users can achieve faster design closure. The flow also incorporates a hierarchical technology to help reduce the design time on large high-performance CPUs. The Innovus Implementation System’s GigaOpt power optimization capability significantly reduces dynamic power consumption for large 5nm chips, while the Tempus ECO Option provides signoff-accurate final design closure using path-based optimization.
Cadence has also optimized its System-Level Verification IP (System VIP) and verification full flow to support the latest AMBA interconnect protocols for ARMv9 IP. The System VIP extensions include new checkers, verification plans and traffic generators to efficiently verify ARM mobile SoC coherency, performance and ARM SystemReady compliance.
The verification full flow, which provides optimal verification throughput for the latest ARMv9 IP, includes the Cadence Xcelium Logic Simulation Platform, Palladium Z1 and Z2 Enterprise Emulation Platforms, Protium X1 and X2 Enterprise Prototyping Platforms, JasperGold Formal Verification Platform, vManager Planning and Metrics, and Perspec System Verifier and Virtual System Platform.
“Cadence has collaborated with ARM on many generations of CPUs and GPUs for mobile IP development, and our latest work expands our support for the recently introduced Armv9 architecture,” said Dr. Chin-Chi Teng, senior vice president and general manager, Digital & Signoff Group at Cadence. “ARM uses our Cadence digital and verification full flow innovations to develop its mobile IP, and with the rollout of ARM’s new CPUs and CPUs, we’re enabling customers to achieve PPA targets to accelerate time to tapeout and providing SystemReady verification and early software bring-up.
The same chip designers are also using the Synopsys Fusion Design Platform, including RTL Architect and Fusion Compiler on the ARMv9 chips for the 5nm tapeouts and early 3nm designs. These include the Fusion Design Platform, Verification Continuum Platform, and DesignWare Interface IP.
"Data is becoming an ever-increasing and important currency in this knowledge-driven world, and its timely, efficient and secure processing is paramount in shaping a safe, information-leveraged future," said Shankar Krishnamoorthy, general manager of the Digital Design Group at Synopsys. "Our broad portfolio of optimized design, verification, IP, software security and software quality solutions have been aggressively co-optimized with Arm to enable a new wave of high-value applications based on the Armv9 architecture, establishing the new benchmark for trustworthy, power-centric performance."
Early adopters of Arm's new mobile solution are using Synopsys' Verification Continuum Platform solutions optimized for Arm, including Virtualizer Development Kit (VDK) with Arm Fast Models for Cortex-X2, Cortex-A710, Cortex-A510 CPUs and Mali-G710 GPUs, VCS simulation, Verdi for hardware and software debug, Verification IP for AMBA on the Synopsys ZeBu Server and HAPS hardware accelerate hardware-software codevelopment.
- ARM splits its Neoverse datacentre server chip designs
- Swiss AI supercomputer to use new Nvidia ARM chip
Popular articles on eeNews Europe