System-in-package consortium for heterogeneous chiplets

July 13, 2021 // By Nick Flaherty
System-in-package consortium for heterogeneous chiplets
A global consortium is aiming to develop system-in-package devices for 5G and AI using heterogeneous chiplets

GlobalFoundries has teamed with the A*STAR Institute of Microelectronics (IME) in Singapore and three other global companies for a consortium on system-in—package (SiP) chiplet technology.

IME will be working with GF, Asahi-Kasei, Qorvo and Toray to develop high density SiP for heterogeneous chiplets in 5G and AI designs.

The consortium will use IME’s expertise in FOWLP/2.5D/3D packaging for lower power consumption and smaller form factors for 5G, artificial intelligence (AI) and high-performance computing (HPC) applications.

This has to address design, processing, and materials challenges. 3D integration can be used for  multiple frequency band operation in 5G devices to integrate numerous devices such as filters, Low Noise Amplifier (LNA)/ RF Switch, and ASICs. This trend is expected to continue in the coming years, and results in increasing board-space consumed by Radio Frequency Front End (RFFE) modules used in 4G, 5G handsets. IME is teaming with consortium members to apply 3D integration technologies to miniaturise RFFE modules for 5G applications.

IME has invested in 3D integration technologies over the years, including Through-Silicon Via (TSV) with key process modules, package integration schemes and design tools for these advanced packaging technologies. This also includes Through-Silicon-Interposer (TSI), fine-pitch multilayer Re-Distribution Layer (RDL), Micro-bumping, Wafer-toWafer (W2W), and Chip-to-Wafer (C2W) bonding, Wafer reconstruction, Thin-wafer handling, and more.

Package integration schemes supported by IME include 3D stacking using TSV first/middle/last followed by C2C, C2W and W2W; 2.5DIC using TSI; RDL-1st Fan-Out-Wafer-Level Packaging (FOWLP); Chip-1st FOWLP; Antenna-in-Package for RF/mmWAve; Ultra-thin Fan-Out Package-on-Package, and more.

IME has developed Package Process Design Kits (PDK) that support these integration schemes with accurate package interconnect models for Signal/Power Integrity, and physical-verification enablement including Package DRC, LVS to facilitate package design signoff. In this consortium, IME will be applying these advanced packaging techniques to deliver package integration solutions for 5G applications.

“Together with our consortium members, we are committed to bringing advanced packaging solutions to the next level. IME's deep capabilities in 3D integration technologies will help accelerate the development of heterogeneous chiplets integration in high performance computing (HPC), 5G and AI applications, to advance the semiconductor industry,” said Prof Dim-Lee Kwong, Executive Director of IME.

“Globalfoundries is delighted to participate in this SiP Consortium for heterogeneous chiplets integration where chips fabricated using GLOBALFOUNDRIES advanced technologies will be integrated using new SiP technologies to miniaturize RFFE modules for 5G applications,” said Dr. Siah Soh Yun, Vice President, TD, of GF.

www.ime.a-star.edu.sg; www.globalfoundries.com

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