Xilinx launches its most powerful FPGA card

November 15, 2021 // By Nick Flaherty
Xilinx launches its most powerful FPGA card
The Xilinx Alveo U55C accelerator card uses the XCU55 UltraScale+ FPGA with 16Gbytes of high speed HBM2 memory for data centres and HPC

Xilinx has launched its most power powerful FPGA accelerator card for data centres and high performance computing (HPC) systems.

The Alveo U55C uses the 16nm XCU55 UltraScale+ FPGA system-on-chip with 16Gbytes of high speed HBM2 memory and 16 lanes of Gen3 PCI Express or 8 lanes of Gen4. This is a single-slot full height, half length (FHHL) form factor with a low 150W max power, compared to the previous U280 which took up two slots.

The $4,395 card is purpose-built for HPC and big data workloads and works with the new Xilinx RoCE v2-based clustering technology. This RDMA over Converged Ethernet (RoCE) allows hundreds of cards to be combined in a cluster with a standard software API and no custom hardware.

“Scaling out Alveo compute capabilities to target HPC workloads is now easier, more efficient and more powerful than ever,” said Salil Raje, executive vice president and general manager, Data Centre Group at Xilinx. “Architecturally, FPGA-based accelerators like Alveo cards provide the highest performance at the lowest cost for many compute-intensive workloads. By introducing a standards-based methodology that enables the creation of Alveo HPC clusters using a customer’s existing infrastructure and network, we’re delivering those key advantages at massive scale to any data centre. This is a major leap forward for even broader adoption of Alveo and adaptive computing throughout the data centre.”

The RoCE v2 and data centre bridging, coupled with 200 Gbit/s bandwidth, the API-driven clustering solution enables an Alveo network that competes with InfiniBand networks in performance and latency, with no vendor lock-in. MPI integration allows for HPC developers to scale out Alveo data pipelining from the Xilinx Vitis unified software platform that can programme the FPGA without using a high level HDL language.

This allows software developers and data scientists to use the adaptive computing of the FPGA through high-level programmability of both the application and cluster. The major AI frameworks like Pytorch and Tensorflow are supported, as well as high-level programming languages like C, C++ and Python, allowing developers to build domain solutions using specific APIs and libraries, or use Xilinx software development kits, to easily accelerate key HPC workloads within an existing data centre.

Next: Using the U55C FPGA card


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