RISC-V app provides verification toolchain

RISC-V app provides verification toolchain

Technology News |
The ImperasDV toolchain combines all the elements for verification engineers working with custom RIC-V processor cores
By Nick Flaherty

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Imperas Software has developed an app that combines all the tool needed for verification of RISC-V processor IP in chip designs.

The RISC-V open standard Instruction Set Architecture (ISA) allows any SoC developer to design and extend a custom processor, while remaining compatible with the growing ecosystem of supporting tools and software.

The ImperasDV app provides a dependable, reference model-based solution for verification that is compatible with the current UVM SystemVerilog methods for SoC verification. This combines the Imperas RISC-V golden reference model, integrated test bench components, test suites and  professional support and training.

SoC verification is estimated to be 50-80 per cent of the total design time and cost, even without including the processor IP. As any SoC team can now develop a custom RISC-V processor optimized for a specific application, they also have to handle the verification, and this can be ten times the complexity of the SoC that is developed around it.

Due to the wide range of configuration options within the RISC-V specifications, the verification task has previously required extensive set-up and time-consuming manual adjustments to the established SoC design and verification flow. This is especially the case when custom extensions or modifications are included during the design, which are often iterated with the common HW/SW co-design as the software driven design style explores additional custom feature optimizations.

The increasing popularity of open-source IP is also contributing to the growth in teams undertaking verification as an in-coming quality inspection as part of initial phase of an SoC project, plus the design option to modify or extend the base core functionality will depend on a working DV framework from the start.

Imperas RISC-V golden reference model is an envelope model that covers the entire RISC-V ISA including privileged mode and supports the latest extensions for crypto (Scalar), Bitmanip, Vector, and DSP/SIMD. This has configurable support for previous specification revisions and drafts and supports user defined custom instructions and extensions.

The integrated SystemVerilog testbench components are compatible with all major EDA environments and provide the C/C++ components for use in C/C++ test benches using Verilator.

A new open standard RVVI (RISC-V Verification Interface) provides integration between RTL, reference model and testbench as well as close-coupled integration for instruction accurate step-and-compare. This also supports multi-hart, superscalar and out-of-order CPU pipelines and provides verification coverage with instruction level analysis and reporting.

The test suites support multiple options for popular ISG (Instruction Stream Generators) such as the RISCV-DV open source ISG developed by the team at Google and the FORCE-RISCV open source ISG maintained by the OpenHW Group. This also includes the Valtrix Systems STING test generator supports pre-integrated Imperas RISC-V reference models to generate portable bare-metal programs containing self-checking architecturally-correct test stimulus. This follows a deal with Valtrix signed last week (see below).

The Imperas Architectural reference test suites including Floating Point, Bitmanip, Crypto, Vector, DSP/SIMD

The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog UVM environment. This covers asynchronous events and offers a seamless, time-saving, transition to debug analysis when an issue is found.

The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. Customers include Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems, plus others yet to be made public.

Next: Valtrix RISC-V verification deal, availability


Imperas last week announced a partnership with Valtrix Systems for RISC-V processor test and validation around the STING bare-metal software tool for design verification of SoC implementations.

Implemented in an architecture agnostic manner, STING supports generation of constrained random, directed or graph-based portable stimulus for multiple IPs. Valtrix have integrated STING with riscvOVPsim, the free RISC-V ISS (Instruction Set Simulator) Imperas launched to support RISC-V software and tools ecosystem development, and to validate and test RISC-V open ISA (Instruction Set Architecture) implementations. With this partnership Valtrix can configure virtual platforms as a verification reference as well as extending the RISC-V envelope model with custom instructions.

“We are encouraged by the developments with STING around riscvOVPsim for RISC-V processors to solve complex test and verification based on commercial grade simulation technology,” said Simon Davidmann, president and CEO, Imperas. “The strength of an ecosystem is close collaborations between partners that lead to better solutions for our mutual customers. With this expanded relationship Valtrix can address RISC-V implementations with custom instructions and model complete RISC-V processor sub-systems as reference virtual platforms.”

“RISC-V is ideal for the latest compute requirements of single-core embedded controllers through to multicore arrays for high performance computing applications,” said Calista Redmond, CEO of RISC-V International. “Companies like Imperas are leading the charge in making SoC design and verification flow easier to further accelerate the mass adoption of RISC-V.”

“The open ISA of RISC-V is at the forefront of the wave of innovation that is stimulating design exploration across all embedded and compute markets,” said Davidmann. “RISC-V offers SoC develops the design freedoms for a custom processor as a unique solution optimized at the point of use, however this shifts the verification task from the few specialist suppliers to all SoC teams. Our new product, ImperasDV provides the efficiency and trusted quality for SoC teams as they step-up to the challenge of RISC V verification, which represents the greatest migration in verification responsibility in the history of EDA.”

The free riscvOVPsimPlus package, including the test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

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