Unified 3D-IC platform boosts chiplet system design
Cadence Design Systems has launched the third generation of its 3D-IC design tool with 3D design planning, implementation and system analysis in a single, unified cockpit.
The Integrity 3D-IC tool, used by R&D lab imec in Belgium, adds system-driven power, performance and area (PPA) for individual chiplets through integrated thermal, power and static timing analysis capabilities.
The unified database across multiple tools allows chip designers creating hyperscale computing, consumer, 5G communications, mobile and automotive applications to achieve greater productivity for 3D and chiplet designs versus a disjointed die-by-die implementation approach. This is increasingly important with the move to 3nm adn 2nm porcess technology nodes (see Samsung article below).
The platform provides system planning, integrated electrothermal, static timing analysis (STA) and physical verification flows, enabling faster, high-quality 3D design closure. It also incorporates 3D exploration flows, which take 2D design netlists to create multiple 3D stacking scenarios based on user input, automatically selecting the optimal, final 3D stacked configuration.
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“With 3D-IC design continuing to gain momentum, there is an increased need to automate the planning and partitioning of a 3D stack die system more efficiently. As the world-leading research and innovation hub in nanoelectronics and digital technologies and through our longstanding collaboration with Cadence, we’ve successfully found automated ways to partition designs to build an optimal 3D stack with increased accessible memory bandwidth that pushes performance and lowers power in advanced-node designs. The integrated memory on the logic flow included in Cadence’s Integrity 3D-IC platform enables cross-die planning, implementation and multi-die STA, which our research teams demonstrated on a multi-core high-performance design,” said Eric Beyne, senior fellow and program director, 3D System Integration at imec.
The common cockpit and database lets chip and package design teams optimize the complete system at the same time, allowing system-level feedback to be incorporated efficiently. A complete 3D-IC stack planning system supports all types of 3D designs, enabling customers to manage and implement native 3D stacking across package design teams and outsourced semiconductor assembly and test (OSAT) companies that use Cadence Allegro packaging technologies.
Direct script-based integration with the Cadence Innovus Implementation System supports high-capacity digital designs with 3D die partitioning, optimization and timing flows with the chiplets, while early electrothermal and cross-die analysis allows early system-level feedback for system-driven PPA.
“Cadence has historically offered customers strong 3D-IC packaging solutions through its leading digital, analog and package implementation product lines,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “With recent developments in advanced packaging technologies, we saw a need to further build upon our successful 3D-IC foundation, providing a more tightly integrated platform that ties our implementation technology with system-level planning and analysis. As the industry continues to move toward different configurations of 3D stacked dies, the new Integrity 3D-IC platform lets customers achieve system-driven PPA, reduced design complexity and faster time to market.”
“To push AI acceleration using optical computing, we’ve consistently leveraged all the latest, innovative trends in the chip design industry—a key innovation being multi-chiplet stacking. In order to build a heterogeneous multi-chiplet stacked design, it is important to have a fully integrated planning and implementation system, which can represent multiple technology nodes in a single cockpit. The Cadence Integrity 3D-IC platform provides a unified database solution with implementation and early system-level analysis capabilities, including timing signoff and electrothermal analysis. It helps us deliver next-generation innovation using optical computing for AI acceleration,” said Yichen Shen, founder and CEO of Lightelligence.
“There are increased requirements for building 2.5D/3D-IC designs with multiple chiplets like logic dies and high-bandwidth memories that are connected with silicon interposer technology. To meet our performance criteria, interposer routing needs automation to be correct-by-construction while taking into account location, shielding and system integrity requirements. The Cadence Integrity 3D-IC platform is well integrated for optimal interposer implementation and system analysis and offers fast, complete system analysis, enabling us to deliver designs that meet memory bandwidth demands for hyperscale computing and 5G communications,” said Tuobei Sun, head of R&D in the Department of Packaging and Testing at SaneChips
Other articles on eeNews Europe
- Samsung looks to 2nm in 2025
- PCIe 6.0 specification approaches release
- Marvell aims for 20 percent growth with 3nm move
- Stratasys acquires Xaar’s 3D printing joint venture
- NeuroBlade raises $83m for compute in memory chip
- Intel backs RISC-V for Nios FPGA processor