Andes adds floating-point, virtual memory support to RISC-V cores

September 27, 2018 //By Peter Clarke
Andes adds floating-point, virtual memory support to RISC-V cores
Andes Technology Corp. (Hsinchu, Taiwan) has added floating point and virtual memory support to its range of RISC-V based processor cores bring the total in the 25 series to six.

The company, which went public in March 2017 on TWSE, introduced the N25 32bit RISC-V and the NX25 64bit RISC-V implementations later that year (see Andes processor cores offered on FDSOI). Now the company has introduced the N25F and NX25F and the A25 and AX25 with the A denoting virtual memory support as well as floating-point.

The N25F and and NX25F have twice the performance of the Cortex-M7 and Cortex-A7, as measured in Whetstone-MIPS per MHz, said Charlie Su, CTO of Andes. In addition support has been brought in for misaligned memory accesses in hardware, which is good for porting existing software from ARM and x86. Without it more than 100 cycles can be needed in the exception handler.

PPA comparison for 25-Series (32-bit). Source: Andes Technology.

The additional cores extend the applicability of the 25 series to networking, storage and data center applications to complement IoT and edge processing.

In an interview with eeNews Europe Su made the point that the company's main focus is now on RISC-V and that the company is playing an active role in the RISC-V Foundation and is a major contributor in terms of architecture extensions. Andes is chair of the Packed SIMD/DSP Task Group and co-chair of the Fast Interrupt Task Group.

PPA comparison for 25-Series (64-bit). Source: Andes Technology.

The company has achieved a number of significant design wins including the Amazon Echo Dot2 courtesy of a MediaTek WiFi chip, as an ADAS controller in the Nissan X-Trail vehicle and in the Nintendo Switch in a Macronix flash memory controller.

Next: Advantages over other RISC-V


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