RISC-V app provides verification toolchain

December 06, 2021 // By Nick Flaherty
RISC-V app provides verification toolchain
The ImperasDV toolchain combines all the elements for verification engineers working with custom RIC-V processor cores

Imperas Software has developed an app that combines all the tool needed for verification of RISC-V processor IP in chip designs.

The RISC-V open standard Instruction Set Architecture (ISA) allows any SoC developer to design and extend a custom processor, while remaining compatible with the growing ecosystem of supporting tools and software.

The ImperasDV app provides a dependable, reference model-based solution for verification that is compatible with the current UVM SystemVerilog methods for SoC verification. This combines the Imperas RISC-V golden reference model, integrated test bench components, test suites and  professional support and training.

SoC verification is estimated to be 50-80 per cent of the total design time and cost, even without including the processor IP. As any SoC team can now develop a custom RISC-V processor optimized for a specific application, they also have to handle the verification, and this can be ten times the complexity of the SoC that is developed around it.

Due to the wide range of configuration options within the RISC-V specifications, the verification task has previously required extensive set-up and time-consuming manual adjustments to the established SoC design and verification flow. This is especially the case when custom extensions or modifications are included during the design, which are often iterated with the common HW/SW co-design as the software driven design style explores additional custom feature optimizations.

The increasing popularity of open-source IP is also contributing to the growth in teams undertaking verification as an in-coming quality inspection as part of initial phase of an SoC project, plus the design option to modify or extend the base core functionality will depend on a working DV framework from the start.

Imperas RISC-V golden reference model is an envelope model that covers the entire RISC-V ISA including privileged mode and supports the latest extensions for crypto (Scalar), Bitmanip, Vector, and DSP/SIMD. This has configurable support for previous specification revisions and drafts and supports user defined custom instructions and extensions.

The integrated SystemVerilog testbench components are compatible with all major EDA environments and provide the C/C++ components for use in C/C++ test benches using Verilator.

A new open standard RVVI (RISC-V Verification Interface) provides integration between RTL, reference model and testbench as well as close-coupled integration for instruction accurate step-and-compare. This also supports multi-hart, superscalar and out-of-order CPU pipelines and provides verification coverage with instruction level analysis and reporting.

The test suites support multiple options for popular ISG (Instruction Stream Generators) such as the RISCV-DV open source ISG developed by the team at Google and the FORCE-RISCV open source ISG maintained by the OpenHW Group. This also includes the Valtrix Systems STING test generator supports pre-integrated Imperas RISC-V reference models to generate portable bare-metal programs containing self-checking architecturally-correct test stimulus. This follows a deal with Valtrix signed last week (see below).

The Imperas Architectural reference test suites including Floating Point, Bitmanip, Crypto, Vector, DSP/SIMD

The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog UVM environment. This covers asynchronous events and offers a seamless, time-saving, transition to debug analysis when an issue is found.

The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. Customers include Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems, plus others yet to be made public.

Next: Valtrix RISC-V verification deal, availability

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.