Cadence Design Systems has developed a verification environment that uses machine learning and AI across a suite of applications to boost coverage and accelerate root cause analysis of bugs.
The Verisium platform integrates natively with the Cadence verification engines and is built on the new Cadence Joint Enterprise Data and AI (JedAI) Platform. It is already being used by chip designers including MediaTek, STMicroelectronics and Samsung.
As chip complexity continues to rise, verification is increasingly a critical path for system design and implementation, often consuming considerably more compute and human resources than any other silicon engineering task.
Cadence says Verisium represents a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that use big data and AI to optimize multiple runs of multiple engines across an entire SoC design and verification campaign. It has already used AI for its JasperGold formal verification tool and its Cerebrus and Optimality design and architectural tools.
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Within Verisium, all the verification data, including waveforms, coverage, reports and log files, are brought together in the Cadence JedAI Platform from repositories in-house, on Github and on Perforce. Machine learning models are built and other proprietary metrics are mined from this data to provide the AI capability.
The initial verification suite includes six apps.
AutoTriage builds ML models that help automate the repetitive task of regression failure triage by predicting and classifying test failures with common root causes, while SemanticDiff compares multiple source code revisions of an IP or SoC, classifies the revisions and ranks which updates are most disruptive to the system’s behaviour to help pinpoint potential bug hotspots.
WaveMiner applies AI engines to analyze waveforms from multiple runs and determine which signals, at which times, are most likely to represent the root cause of a test failure, while PinDown integrates with JedAI, Github or Perforce revision control systems to build ML models of source code changes, test reports and log files to predict which source code check-ins are most likely to have introduced failures.
The Debug app provides a holistic debug solution from IP to SoC and from single-run to multi-run, offering interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies. This is natively integrated with the JedAI Platform and other Verisium apps to enable AI-driven root cause analysis with the support of simultaneous automatic comparison of passing and failing tests.
Pulling all this together, the Verisium Manager app provides full flow IP and SoC-level verification management with verification planning, job scheduling, and multi-engine coverage natively onto the JedAI Platform and extends it to support AI-driven test suite optimization to improve compute farm efficiency. It also integrates directly with other Verisium apps, enabling interactive push-button deployment of the complete Verisium platform from a unified browser-based management console.
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“AI and big data are transforming the world around us,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “To realize this transformation in our core EDA business, we must build new technologies that optimize across multiple runs and engines. With the Verisium platform, we enter a new era of AI-driven verification built on the Cadence JedAI Platform. Our journey is just beginning, but users are already seeing dramatic improvements in their verification productivity and efficiency using the Verisium platform.”
“Functional verification has continued to be a major concern to address the rapidly growing complexity of IP and SoC designs in STM32 Microcontrollers,” said Mirella Negro Marcigaglia, STM32 Digital Verification Manager at STMicroelectronics.
“Cadence’s data-driven functional verification platform and apps leveraging AI technology are a very promising approach to contain this problem. ST and Cadence have a strong vision match, which has led to a tight collaboration to deploy multiple Verisium apps at ST. We have already observed a significant boost to functional verification productivity, leveraging Verisium AutoTriage, SemanticDiff and WaveMiner. Using the Verisium apps and the Cadence JedAI Platform, we aim to quickly achieve a dramatic productivity improvement in triaging and localizing bugs on our IP and SoC designs.”
“Our tight collaboration with Cadence confirms the Verisium platform’s groundbreaking ability to automatically accelerate the effort to root cause bugs, and we are working with Cadence to expand deployment across our IP and SoC verification teams,” said Chinh Tran, Deputy General Manager, Silicon Product Development, MediaTek.
“As SoC complexity continues to grow, SoC-level verification has become a rate-limiting step in our tapeout schedules. We see a great opportunity to leverage AI and big data to dramatically improve design and verification productivity. We are working closely with Cadence to deploy the Verisium platform on our mobile SoC designs and are already seeing impressive results to automatically triage and root cause bugs,” said Brian Choi, Corporate VP, Samsung Electronics.
Verisium is part of the Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform and the Helium Virtual and Hybrid Studio.
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