ARM has disclosed more details of its Neoverse V2 high performance processor core, codenamed Demeter and the first to use the ARMv9 architecture, while planning the next version for 2023.
One of the first customers for the V2 core is Nvidia for the 72 core Grace CPU, which Nvidia will discuss next week. The underlying ARMv9 technology was launched in March last year.
The architecture of the V2 core has been optimised for specific applications in the data centre, most notably the BERT machine learning framework. This involved tuning the flow of the BF16 instruction to boost performance as well as doubling the instruction cache (icache) for the core to 2Mbits. It has also increased the vector performance of the core with four lanes of 128bit wide interconnect for the scalable vector extensions (SVE2).
“We have added icache coherency, workload specific optimisation eg BERT, larger cache and 48bit physical addressing to the V line for cloud workloads,“ said Dermot O’Driscoll, vice president of product solutions. “We have been tuning the microarchitecture against specific workloads and we are seeing modelling data that looks really good,” said Brian Jeff, senior director of product management at ARM.
ARM points to V1 designs by Amazon for the Graviton3 being used in the data centre as well as the Ampere Max and Ultra Max and Alibaba’s 128 core Yitian 710. A series of V2 designs are expected over the next year.
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The next generation core is codenamed Poseidon and unless there is a dramatic change in the naming system, this will be the Neoverse V3. ARM is already talking about the Neoverse N3 core, where it has 20 partners working on the core and this will include the CXL3.0 standard for memory interconnect.
“V2 is available to our customers and we will provide more details on the next core when appropriate and will talk about solutions when they get close to deployment,” said Chris Bergey, senior vice president and general manager of the Infrastructure Line of Business.
This is being driven by the need for customisation for workloads in the data centre, combining CPU cores with AI accelerator cores and intelligent interconnect, either as a single chip or as chiplets.
Here the interconnect is key, and the V2 and V3 will use the CMN-700 interconnect, based on ARM’s AMBA Coherent Hub Interface (CHI). This will work with the CXL memory interconnect standards and with the UCIe chiplet protocol where ARM is a founding member alongside Intel and AMD.
Related CXL3.0 and UCIe articles
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- Chiplet standards group launches
- Verification supports chiplets using UCIe standard
However ARM is dismissive of the challenge from customised RISC-V cores in the data centre despite recent high profile designs.
“We have a lot of respect for what the RISC-V team are doing and that is driving healthy competition” he said. “We have a long history of supplying fully verified, fully validated cores and customers coming back with silicon and going straight to volume,” he said. “We believe we are in a pretty good place, we don’t see any commercial challenges.”
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“We don’t see RISC-V as a significant competitor in the data centre right now or in the near future,” said Bergey.
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