Automating complex chip design signoff
Cadence Design Systems has launched a design closure tool to tackle the growing challenge of larger, more complex chip and chiplet-based designs.
Cadence Certus Closure automates and accelerates the complete design closure cycle from weeks to overnight. Renesas and MaxLinear are early users of the tool that provides signoff optimization through routing, static timing analysis (STA) and extraction.
The tool supports the largest chip design projects with unlimited capacity while substantially improving productivity by up to 10X versus manual processes for full chip assembly, static timing analysis, and optimization and signoff with 100s of views, taking designers months to converge.
The Cadence Certus Closure eases the design signoff closure bottlenecks and complexities that come with developing today’s emerging applications such as hyperscale computing, 5G communications, mobile, automotive and networking.
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It provides a fully automated environment using distributed cloud computing for concurrent, full-chip optimization through an engine shared with the Cadence Innovus Implementation System and the Tempus Timing Signoff tools, eliminating iterative loops with block owners while enabling designers to make quick optimization and signoff decisions.
The tool is also tightly integrated with the Cadence Integrity 3D-IC Solution to allows designers to close inter-die paths across heterogenous process dies
Used with the Cadence Cerebrus Intelligent Chip Explorer, designers can experience additional productivity improvements from block-level to full-chip signoff closure.
The tool provides flexible restore and replacement of only the changed portions of the design, further accelerating final signoff while the fully automated flow reduces the need for multiple, lengthy iterations across multiple teams. The SmartHub interactive GUI allows cross-probing for detailed timing debug to drive last-mile design closure.
“With the Cadence Certus Closure Solution, our engineering team observed 6X faster chip-level signoff closure turnaround time versus current methodologies, improving overall productivity. Following this success, we plan to adopt the solution for the development of our latest designs,” said Yukio Minoda, Senior Principal Engineer, Digital Design Technology Department, Shared R&D EDA Division at Renesas Electronics.
“Today’s design teams often spend five to seven days per iteration to meet chip-level signoff timing and power requirements, and previous methodologies failed to deliver the team collaboration and user experience needed for efficient design closure,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence.
“It is imperative for us to deliver our high-performance and low-power analog and mixed-signal products on schedule,” said Dr. Paolo Miliozzi, vice president, SoC Design and Technology at MaxLinear. “Full chip-level signoff closure is one of the biggest bottlenecks our engineering team faces when working tirelessly to meet customer delivery commitments. With the Cadence Certus Closure Solution, our engineering team can experience overnight full chip-level signoff closure via its concurrent optimization and signoff capabilities, improving overall engineering team productivity. The solution’s ability to automate the whole optimization and signoff flow—STA, routing, and extraction—empowers our engineering team to achieve greatly improved design success, realize untapped power saving of up to 5% and get to market faster.”
The Cadence Certus Closure Solution supports the company’s Intelligent System Design strategy, which enables design excellence.
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