Boost for chiplet standards group
VeriSilicon and Astera Labs have joined the Universal Chiplet Interconnect Express (UCIe) industry consortium, boosting the support for open standards to connect silicon die in a package.
VeriSilicon is the leading IP supplier in China and one of the first enterprises in mainland China to join the organization. The first generation UCIe 1.0 open specification defines the interconnect between chiplets within a package, and Verisilicon will use it for IP for chips for tablets and laptops, autonomous driving and data centres. The company will also be working on the development of the next generation of UCIe technology and says it plans to have the first commercial chiplet IP available.
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At the same time US connectivity startup Astera Labs has also joined the consortium. The company is developing technology for the CXL and PCI express standards that are used by UCIe.
The consortium was founded last month by Advanced Semiconductor Engineering, (ASE), AMD, ARM, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and foundry TSMC.
“UCIe is the culmination of learnings over many years implementing on-package interconnects and the time is right for industry standardization,” said Dr Debendra Das Sharma, Intel Senior Fellow. “We are excited that Astera Labs is joining the consortium and working to develop products such as UCIe Retimers and UCIe Memory Accelerators.”
According to the latest IPnest statistics, VeriSilicon ranked 1st in mainland China and 7th worldwide among semiconductor IP suppliers. It has six categories of in-house processor IPs, including Graphics Processor Unit (GPU) IP, Neural Network Processor (NPU) IP, Video Processor Unit (VPU) IP, Digital Signal Processor (DSP) IP, Image Signal Processor (ISP) IP and Display Processor IP, as well as leading chip design capabilities.
VeriSilicon has launched its own a high-end application processor platform based on chiplet architecture, with a 12nm SoC version taping out. An upgraded chiplet-based version is in progress.
“Tablets/laptops, autonomous driving and data centres stand out as the first areas where chiplets will be adopted,” said Dr. Wayne Dai, Chairman, President and CEO of VeriSilicon. “Tablets/laptops require more heterogeneous processor IPs with different functions, data centres need to integrate multiple general-purpose high-performance computing modules, and automotive-grade chiplets can significantly improve the iterative efficiency of automotive chips and reduce the potential security risks associated with single chip failure, which are all ideal use cases for chiplets.
“VeriSilicon’s efforts in chiplet-based projects over the years have not only facilitated the industrialization of chiplets, but also elevated our semiconductor IP licensing services and one-stop custom silicon services to new heights. VeriSilicon will be likely to be one of the world’s first companies to bring commercialized chiplet products to market,” he said.
“The new UCIe specification enables innovative chiplet solutions to optimize power, performance, cost, and time to market of large SoCs for data centres as well as enhanced resource sharing and pooling across servers,” said Jitendra Mohan, CEO of Astera Labs. “We are excited to support this new industry effort with our proven expertise in intelligent CXL and PCIe interconnects and look forward to expanding our purpose-built connectivity solutions portfolio to include products based on the UCIe standard.
www.verisilicon.com; www.asteralabs.com; www.uciexpress.com
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