Samsung takes DRAM 512-pins wide
The chip is implemented in a manufacturing process technology somewhere between 50- and 59-nm and Samsung is also due to present a paper related to wide I/O DRAM technology at the 2011 International Solid-State Circuits Conference being held from February 20 to 24 in San Francisco.
To boost data transmission, the wide-I/O DRAM uses 512 pins for data input and output compared to the previous generation of mobile DRAMs, which used a maximum of 32 pins. Including pins for commands and power supply and its regulation the WIO DRAM is designed to have ip to 1,200 pins.
Samsung did not indicate whether it intends to offer the 1-Gbit WIO DRAM as a packaged part or to use it as a bare die in multi-chip packages. Nor did Samsung state when engineering samples of the 1-Gbit WIO DRAM would be available or it would be in volume production.
Nonetheless, as a result of the extreme I/O the 1-Gbit WIO DRAM can transmit data at 12.8-Gbytes per second, increasing the bandwidth of mobile DDR DRAM eightfold, while reducing power consumption by approximately 87 percent. The bandwidth is also four times that of LPDDR2 DRAM, which is approximately 3.2-Gigabytes per second, Samsung said.
To follow on from the WIO DRAM launch Samsung is planning for a 20-nm class 4-Gbit WIO mobile DRAM to become available in 2013,
"Following the development of 4-Gbit LPDDR2 DRAM last year, our new mobile DRAM solution with a wide I/O interface represents a significant contribution to the advancement of high-performance mobile products," said Byungse So, senior vice president, memory product planning and application engineering at Samsung Electronics, in a statement.