Toshiba redefines the flip-flop for lower power

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By eeNews Europe

A typical SoC uses 100,000 to 10 million flip-flops, and each typical flip-flop incorporates a clock buffer to produce a clock inverted signal required for the circuit’s operation. When triggered by a signal from the clock, the clock buffer consumes power, even when the data is unchanged. While clock gating is widely used to cut delivery of the clock signal to unused blocks, after applying the clock gating the flip-flop active rate – a measure of data change rate per clock – is only 5-15%, indicating that there is still plenty of room for further power reduction.

In order to save power, Toshiba changed the structure of the typical flip-flop and eliminated the power-consuming clock buffer. This approach brings with it the problem of data collision between the data writing circuitry and the state holding circuitry in the flip-flop, which Toshiba overcame by adding adaptive coupling circuitry to the flip-flop.

A combination of an nMOS transistor and a pMOS ransistor, this circuitry adaptively weakens state-retention coupling and prevents collisions. Despite the addition of the adaptive coupling circuitry, overall simplification of the basic flip-flop configuration reduces the transistor count from 24 to 22, and the cell area is less than that of the conventional flip-flop.


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