Verix DFT is deployed throughout the design process: first during RTL design, as part of addressing asynchronous set/reset, clock and connectivity issues early, then after scan synthesis, to check for scan chain rule compliance, and last following place & route to assess and correct issues with scan-chain reordering or netlist modification.
The company says the new tool can reduce static sign-off time by several weeks, thanks to a lower setup time, runtime speedup, and the reduced engineering debug and violation fixing due to consolidated reporting. In a single run, the tool can analyze multiple ATPG partitions, eliminating the time-consuming process of running DFT static sign-off for each partition separately. The tool supports multiple constraint sets, where each constraint set corresponds to the ATPG pattern type, and can analyze these constraint sets across multiple test modes.
Verix DFT’s unique characteristics enable designers to prepare their RTL and gate-level designs for the highest possible quality ATPG pattern generation and silicon success. In addition to its multimode analysis capability, Verix DFT can handle multimillion-gate designs in minutes, with full chip capacity and a low peak memory footprint. Real Intent says it uses the industry’s most comprehensive array of rules to help ensure high coverage at all design stages, including asynchronous set/reset, clock, scan-chain, flip-flop, port & connectivity sign-off rules, and a variety of basic setup checks.