Open source consultancy Collabora has added the H.265 video coder and decoder to i.MX 8M processor from NXP. Several boards using the new microcontroller are being launched in the next few weeks.
“One of the platforms we have been working on at Collabora is VeriSilicon's Hantro codec,” said Benjamin Gaignard, senior software engineer at Collabora in France.
This video IP is already ported to the NXP’s i.MX8 and other popular SoCs from Rockchip and Microchip and is marketed as a small and power efficient device, but it also has a feature that makes it specially attractive for open source developers as it is a stateless accelerator.
Stateless devices do not need firmware to operate, making them more robust and better suited for open source platforms, where having full control over the system is desirable. In this case, the support is split in two: a kernel driver provided by a Video4Linux Hantro driver, and a userspace component, which can be provided by frameworks such as GStreamer and FFMPEG.
“Our recent efforts on the Hantro kernel driver have resulted in the addition of H.264 decoding support and multiple performance improvements. Continuing this work, we are now introducing High Efficiency Video Coding (HEVC), also known as H.265, decoding support on NXP's i.MX 8M chipset,” said Gaignard.
Unlike the currently supported codecs (JPEG, MPEG-2, VP8 and H.264), HEVC doesn't rely on the G1 hardware block but on the second video processor unit, the G2.
For this first step, the driver supports the basic HEVC features up to level 5.1. Enhanced features like 10bits depth per sample with 4:2:0 chroma sampling, scaling or tile decoding could be added later. Another possible evolution is to take benefit of the hardware capability to use compressed buffers to limit the memory bandwidth consumption.
Supporting HEVC on the Hantro driver will help mature the HEVC V4L2 stateless API enough to be able to remove it from the staging directory says Gaignard. Getting