RISC-V verification IP looks to drive SoC designs

December 10, 2020 // By Nick Flaherty
RISC-V verification IP looks to drive SoC designs
Imperas is providing free simulator, architectural validation test suites and SystemVerilog components for verifying RISC-V system-on-chip designs

Imperas Software in the UK has added key elements to its RISC-V processor hardware design verification tools that it says will help the development of system-on-chip devices.

The release includes an enhanced reference model with SystemVerilog encapsulation / integration and new test bench blocks, a new riscvOVPsimPlus free simulator and a range of RISC-V architectural validation tests for the ratified and soon to be ratified RISC-V ISA extensions.

“The open standard ISA of RISC-V is enabling system designers to explore new innovations with optimized processors, which in turn is driving all SoC adopters to expand the design verification plans to cover the specialist processor DV tasks,” said Simon Davidmann, CEO at Imperas Software Ltd. “We are proud of the success the Imperas RISC-V golden reference model has achieved and see the new Verification IP and test suites as a way to help all SoC teams address the challenges of processor DV through the adoption of SystemVerilog test benches with step-and-compare methodologies for processor DV.”

The riscvOVPsimPlus RISC-V reference model and simulator has been widely adopted across the RISC-V verification ecosystem and has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options. The updated model includes all the full standard CLIC features, Debug Module / Mode, “H” Hypervisor simulation, and also 'near-ratified' ISA extensions for Vector “V”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions.

To support the SystemVerilog encapsulation of the reference model, the RISC-V Processor Verification IP (VIP) package includes example SystemVerilog supporting components and modules for interfacing and synchronization between the Imperas RISC-V golden reference model and the RTL core under test in a step-and-compare verification flow.

This approach covers the important aspects of asynchronous events and debug mode operation while also supporting the DV engineer’s active investigation directly at the point of interest during test failure analysis and resolution.


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