Socionext taps Synopsys 5nm memory IP for datacentre AI

January 15, 2021 //By Jean-Pierre Joosting
Synopsys and Socionext expand collaboration on 5nm IP
Chip designer Socionext will use the Synopsys DesignWare HBM2/2E memory interface IP in its 5nm AI Engine and Accelerator for datacentre applications

Chip design house Socionext is working with Synopsys on using HBM2E memory interface IP for a 5nm AI and high-performance computing (HPC) chip for datacentre applications.

Socionext selected HBM2E IP from Synopsys, operating at 3.6 Gbps, to meet the stringent capacity, power, and compute performance requirements of its AI engine and accelerator system-on-chip (SoC). Synopsys says he IP provides efficient heterogeneous integration with the shortest 2.5D interposer package routes.

“As a global leader in SoC solutions with differentiated functionalities, we face very tight delivery deadlines,” said Yutaka Hayashi, vice president of Automotive & Industrial Business Group at Socionext. “By leveraging Synopsys’ DesignWare HBM2E IP and integrated full-system multi-die design platform, Socionext can deliver world-class high-performance, high-capacity and power-efficient SoCs on the 5-nanometer FinFET process to the market. We are also collaborating with Synopsys on using their next-generation DesignWare IP including HBM3.”

With an aggregated bandwidth of 460 gigabytes per second, the DesignWare HBM2E PHY IP delivers the required massive compute performance of SoCs in advanced FinFET processes. The HBM2E IP is part of Synopsys' comprehensive memory interface IP solution that includes DDR5/4/3/2 and LPDDR5/4/4X/3/2 IP, which have been validated in hundreds of designs and shipped in millions of SoCs.

“As the leading memory interface IP provider, Synopsys provides innovative companies, like Socionext, with a highly competitive HBM2/2E IP solution that addresses the aggressive power and memory bandwidth requirements of advanced high-performance computing SoCs,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “Synopsys’ silicon-proven DesignWare HBM2/2E IP, with over 25 design wins and customers in volume production, enables designers to confidently integrate the IP into their SoCs with less risk and achieve a faster path to silicon success.”

The Synopsys DesignWare HBM2/2E IP in a wide range of processes from 16nm to 5nm is available now.

www.socionext.comwww.synopsys.com/designware

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