Graphcore’s ‘Colossus’ chip due before end of year
Graphcore’s intelligent processor unit (IPU) will be shipping to early-access customers before the end of 2017 and more general availability will start early in 2018, Knowles stated.
Knowles provided the information in a talk to the Research and Applied AI Summit (RAAIS). RAAIS is a community for entrepreneurs and researchers who accelerate the science and applications of AI technology.
Knowles said he would not provide a complete description of Graphcore’s Colossus but instead discussed the desirable characteristics for a machine intelligence processor adding that it needed to be an architecture that was not bandwidth bound and one that would be able to target desirable computational models for 20 years hence. While it needed to be good at supporting neural networks it should also be able to address concerns of higher abstraction that may become more relevant, Knowles argued.
Slide from Simon Knowles’ RAAIS presentation.
However, in passing he said that Colossus would support a computational model called “bulk synchronous parallel.” This divides processor functioning into two alternating phases; one is independent processor core calculation with local memory, and the second is reserved for exchange of information between processor cores.
Next: Colossal details and video
Knowles did flash up a slide that showed that Colossus will have more than 1,000 processors on a very large die fabricated in 16nm FinFET technology. Two processors will be bundled on a PCIe card and designed to be capable of deployed in large arrays. The chip will use no external memory and the whole model stays on chip during operation, Knowles said. The processor cores will use mixed-precision floating point; 16-bit floating point for multiplications and 32-bit for accumulation.
Slide from Simon Knowles’ RAAIS presentation.
Knowles said that in terms of deep neural network (DNN) Colossus would perform “well beyond” Nvidia’s Volta and Google’s four-chip TPU-2 component.
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