Octocore SPARC v8 chip for space designs

April 21, 2021 // By Nick Flaherty
Octocore SPARC v8 chip for space designs
The GR765 processor being designed by CAES Gaisler in Sweden is based around eight LEON5FT SPARC cores with SpaceWire, CAN-FD and Ethernet interfaces for space designs

CAES Gaisler in Sweden is to design a next generation eight core fault tolerant microprocessor for satellite and other space systems.

The 300MHz GR765 microprocessor will be built around eight LEON5FT Fault Tolerant processor cores and is part of a project that is inviting industrial input.

The first development phase of the GR765 is funded through Element 2: Make of the General Support Technology Programme (GSTP) at the European Space Agency (ESA) and is co-funded by CAES and the Swedish National Space Agency (SNSA). Element 2 sponsors the design, development and demonstration of activities based on industry proposals. In doing so, GSTP encourages more ideas and partnerships.

”The GR765 Microprocessor builds on the success of the GR740 quad-core LEON4FT Microprocessor and contains eight LEON5FT processor cores, which is the latest and most powerful LEON processor so far,” said Mike Kahn, President and CEO of CAES. “Its architectural improvements and octa-core implementation will provide a four-time increase in computational performance when run at the same frequency as previous generation microprocessors. Work is ongoing to improve the maximum operating frequency, further enhancing the performance. With these significant improvements, new, more advanced and data-demanding computations will be possible for payload and platform applications. The first development phase of GR765 Microprocessor will result in engineering samples expected in 2022, with flight production in 2024.

The LEON5 architecture is based around the SPARC v8 instruction set for compatibility with the previous LEON parts and sapce-qualified software, and combines a 12-port SpaceWire router, 10/100/1000 Mbit Ethernet interfaces, 6.25Gbit/s serial links, 33MHz PCI 2.3 initiator/target interface and CAN-FD and DDR2 and DDR3 memory interfaces.

The GR765 is immediately supported by development tools such as the GRMON software debugger and various compilers and operating systems and a qualified boot loader for flight.

 

CAES Gaisler, part of the UK's Cobham group, has a range of processor technologies for space designs, from SPARC to RISC-V, with IP core building blocks, radiation hardened components, flight software & development tools, development hardware, test equipment and services.

“The enhancements of the GR765 address the ever-increasing demands of payload data processing, but also for mission critical control applications such as on-board-computers with integrated GNSS receivers or sensor and image processing for autonomous planetary landing and rover application," said Roland Weigand, Microelectronics Section at the European Space Agency.

“Our customers appreciate the smooth migration from one performant LEON generation to the next, reusing their software and leveraging their past investments,” said Sandi Habinc, General Manager of CAES Gaisler. “The software compatibility and a common development environment makes it easy for a design team, already familiar with the LEON, to quickly come up to speed.”

www.gaisler.com

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The 300MHz GR765 microprocessor will be built around eight LEON5FT Fault Tolerant processor cores by CAES Glaiser in Sweden

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