AI drives big data analytics for chip design
Synopsys has developed a suite of tools that use machine learning to analyse the gigabytes of data that are used for complex system-on-chip designs.
The DesignDash works with the Synopsys Digital Design Family of tools and DSO.ai AI-driven design-space-optimization tool to provide a deeper understanding of run-to-run, design-to-design and project-to-project trends, and enhanced collaboration in the SoC development process.
The cloud-native technology will also be combined with the Synopsys lifecycle tools that take data from chip in the field, and data from fab equipment during the manufacturing.
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“The design flow has always been opaque, tracking the design process is very hard,” said Mark Richards product marketing manager. “Engineers have their own homegrown systems such as scripting systems that really distract from the core task of designing chips. There are thousands of tool runs producing timing data, library data and metrics.”
“We want to take the big data, capture it efficiently and do something with it, do deep analysis, tame the data. We can also look at other projects and use the learning from those to drive better design decisions as we go forwards,” he said.
Structure of DesignDash
There are three main elements to the DesignDash looking at metrics, analytics and streams of log data.
“It goes beyond ML, there are other techniques,” said Richards. “At Synopsys we have the entire suite of products and the data is integrated automatically. We work with standard industry databases and the data is curated and put into the dash database
“We suck the metric data out of the tools once it has finished a step and parse that into a MongoDB. For the analytics we look inside the database for the entire timing graph and extract the analytics, extract the nets and cells into an [Amazon] S3-compatible database – then connect and create an offline version of the data. It isn’t tied to Amazon you can use Google or Azure,” he said.
“Our R&D team has developed a number of models on their own data, including connectivity, and use ML to predict what might happen in the tool flow. We can then create apps that for example apply suggested constraints on timing and the models continue to train over time,” he said. “You can also add in your own ML models with a Python interface for custom workflows and there are rule-based workflow that work out of the box and are shareable.”
“This means I can start to find trends, do data mining and look at how to improve the design flow. I can look across the whole flow and look at causation, why things happened as they did. I can build a view of the chip, understand what isn’t converging, how far out parts the design are so I can apply more resources
This is particularly useful for resource planning. “This provides one [data] scraping methodology, reporting results across the company in the same way with a codified workflow,” he said.
Log stream data
DesignDash is also designed to work with the DSO.ai AI-based tool. When DSO gets stuck with poor RTL or needs a good starting point, DesignDash can provide new starting points to accelerate the time to get to a good solution. This uses a standard JSON table format and so can work with third party test flows via a couple of lines of the TCL scripting language, says Richards.
The tool also has links to the signoff database.
“We have a log stream which is insight from the tool which allows me to drive a stream from the tool and in real time I can start to see trends to see what the different design engines are doing, for example if the flow is not going to converge it can flag a warning,” he said.
While DesignDash is designed to work natively with other Synopsys tools, it also needs to work with third party tools.
“We are in the exploratory phase in making this a standard,” said Richards. “We do work on the Titan committee so that kind of information is being suggested by customers to standardise a logstream interface with standard markers, such as the energy, how hard an engine is working.”
This is also not just about the pre-silicon design tools but also the fab equipment data and the data from the field from the product lifecycle management (PLM) tools.
“We are starting to build out this concept of a data continuum with pre-silicon insights from DesignDash and post silicon from the PLM as well as the fab data,” he said. “It is being worked towards, it’s a big project but it is definitely on the horizon.”
DesignDash customers
DesignDash is already used by a number of customers, including Japanese fabless design house SocioNext that includes the former system LSI businesses of Fujitsu and Panason, a large US IDM and a large European IDM. Synopsys is the primary EDA supplier to Intel in the US and a key supplier to STMicroelectronics in Europe for full-chip static timing analysis, formal equivalence checking and signal-integrity signoff tools as well as timing sign-off for low-power and high-performance system-on-chip (SoC) designs.
“As a leading supplier of SoCs that are powering and transforming numerous high-impact industries, we pride ourselves on being able to push the limits of achievable device performance while also accelerating our customers’ time-to-market,” said Hiroshi Ikeda, director, Methodology Development Office, Global Development Group at Socionext. “We’re very excited by the Synopsys DesignDash analytics solution as a systematic way to capture, consume and evaluate our vast design activity in a scalable way, enabling us to share and transfer expert knowledge across our worldwide design teams to enhance productivity and efficiency.”
“The semiconductor industry needs a dramatic improvement in design process productivity. Improving the quality and speed of engineering decisions with a comprehensive EDA data analytics platform is a critical step in this direction,” said Sanjay Bali, vice president of Marketing and Strategy for the Silicon Realization Group at Synopsys. “Synopsys DesignDash unlocks the potential of the significant and growing volumes of EDA metrics and design-flow data, heralding a new era in smarter IC design by deploying an expanse of advanced data analytics and targeted machine learning to effectively guide design teams to achieve or exceed their product goals and schedules.”
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