Open source chip programme expands to 90nm FDSOI

Open source chip programme expands to 90nm FDSOI

Business news |
By Nick Flaherty

Google is extending its open source chip development programme with US foundry Skywater Technology to a 90nm FDSOI process.

Unlike a traditional CMOS bulk process, FD SOI uses a thin layer of insulator material between the substrate and the upper silicon layer. This thin oxide process allows the transistor to be significantly thinner than in the BULK process, allowing the device to be “fully depleted,” and simplifying the fabrication process. This extra insulation greatly reduces parasitic current leakage and lowers junction capacitances, providing improved speed and power performance under various environmental conditions.

The SKY90-FD process stack has five thin copper base metal layers for the main interconnect and two extra thicker aluminium metal layers capable of conducting higher currents.

Google and Skywater are working on an open source process design kit (PDK) for SKY90-FD, SkyWater’s commercial 90nm fully depleted silicon on insulator (FDSOI) CMOS process technology. This is based on MIT Lincoln Laboratory’s 90 nm commercial FDSOI technology, and enables designers to create complex integrated circuits for a diverse range of applications.

ST, GlobalFoundries and Soitec have also been developing FD SOI process technology down to 22nm in Europe, and are looking to extend this below 10nm.

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Over the last two years, Google and SkyWater Technology have developed an open source PDK for the 130nm process, and have run a series of no-cost manufacturing shuttles for developers in the open source hardware ecosystem.

To date, Google has sponsored six shuttles on the Efabless platform, manufacturing 240 designs from over 364 community submissions with 90 in the last shuttle run from 24 different countries.

Google is planning to release the 90nm PDK over the coming months under the Apache 2.0 license and organize additional Open MPW shuttles to manufacture open source designs through Efabless.

This allows developers to explore different performance, power and area trade offs with existing or new designs with minimal cost, while researchers can reproduce research designs on different technologies to produce diverse figures of merit. Tool maintainers can also generalize their technologies’ backends to support more than one process. 

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