Avery, CoMira team for UCIe chiplets
Avery Design Systems has teamed up with CoMira Solutions in the US to enable chiplet design using the UCIe (Universal Chiplet Interconnect Express) die-to-die interface standard.
The combination of Avery’s verification IP (VIP) and functional verification platform and CoMira’s high-speed protocol stack controller technology currently under development will provide an efficient approach to for the design and verification of multi-die systems using the UCIe standard. Avery’s offering includes high-quality models and test suites that support pre-silicon verification of systems using UCIe.
UCIe was announced earlier this year as a mean to provide interoperability of chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. The focus of the initial specification (Version 1.0) covers the UCIe Adapter and PHY including die-to-die I/O physical layer, Die-to-Die protocols, and software stack which leverage the well-established PCI Express (PCIe) and Compute Express Link (CXL) industry standards in addition to a protocol-agnostic raw transfer mode.
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“CoMira is leveraging its extensive experience in high-speed connectivity IP to provide a reliable and easy-to-integrate UCIe protocol stack technology for multi-die systems. By supporting UCIe for connectivity within the chiplet architecture, and CXL and PCIe for external interfaces, we provide the necessary element for full chiplet connectivity,” said Qasim Shami, founder and CEO of CoMira Solutions. “Avery provides the ideal verification environment to allow pre-silicon validation for the entire chiplet system.”
“A key to success for any standard is a broad and robust ecosystem. Avery’s experience in enabling critical technology that is compliant with emerging standards accelerates timely, accurate design and verification to help meet the market requirements,” said Chris Browy, vice president sales and marketing at Avery.
Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its UCIe offering supports standalone UCIe die to die adapter and LogPHY verification along with integrated PCIe and CXL VIP to run over the UCIe stack. In addition to UCIe models it provides comprehensive protocol checkers, coverage, reference testbenches, and compliance test-suites utilizing a flexible and open architecture.
Avery is in the process of being acquired by Siemens EDA in the next couple of months.
www.avery-design.com; www.comira-inc.com
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